tree b177e8e05649ba7da7f8f7dcfe309fb29b7aef68
parent fcc7fe425183f9ec95fba33d041eb359d0a3a598
author Anatolij Gustschin <agust@denx.de> 1360281829 +0000
committer Wolfgang Denk <wd@denx.de> 1362813782 +0100

mpc512x: Adjust the DRAM init sequence to the datasheet spec

Do maintain a 200 usecs period of stable power and clock before
asserting the CKE signal and sending commands, have at least 200
DRAM clock cycles pass after initialization before data access.

Signed-off-by: Anatolij Gustschin <agust@denx.de>