tree 9ffbad4eb997c0c7813a80bf35c7efa61f73fc15
parent 35e47b7132fa515e32189077ec7b80090562c709
author Marek Vasut <marex@denx.de> 1439246949 +0200
committer Marek Vasut <marex@denx.de> 1440323779 +0200

arm: socfpga: Fix delay in freeze controller

Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the problem.

Instead of permanently lowering the delay, calculate the correct delay
based on the original comment, that is, obtain EOSC1 frequency and use
it to calculate the precise delay.

Signed-off-by: Marek Vasut <marex@denx.de>