// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
 * Copyright 2022 Broadcom Ltd.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,bcm63158", "brcm,bcmbca";
	#address-cells = <2>;
	#size-cells = <2>;

	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		B53_0: cpu@0 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_1: cpu@1 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_2: cpu@2 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		B53_3: cpu@3 {
			compatible = "brcm,brahma-b53";
			device_type = "cpu";
			reg = <0x0 0x3>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		L2_0: l2-cache0 {
			compatible = "cache";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&B53_0>, <&B53_1>,
			<&B53_2>, <&B53_3>;
	};

	clocks {
		u-boot,dm-pre-reloc;
		periph_clk: periph-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};

		hsspi_pll: hsspi-pll {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-mult = <2>;
			clock-div = <1>;
		};

		uart_clk: uart-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};

		wdt_clk: wdt-clk {
			compatible = "fixed-factor-clock";
			#clock-cells = <0>;
			clocks = <&periph_clk>;
			clock-div = <4>;
			clock-mult = <1>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	axi@81000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x81000000 0x8000>;

		gic: interrupt-controller@1000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
			reg = <0x1000 0x1000>,
				<0x2000 0x2000>,
				<0x4000 0x2000>,
				<0x6000 0x2000>;
		};
	};

	bus@ff800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0xff800000 0x800000>;
		u-boot,dm-pre-reloc;

		uart0: serial@12000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x12000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&uart_clk>, <&uart_clk>;
			clock-names = "uartclk", "apb_pclk";
			status = "disabled";
		};

		leds: led-controller@800 {
			compatible = "brcm,bcm6858-leds";
			reg = <0x800 0xe4>;

			status = "disabled";
		};

		wdt1: watchdog@480 {
			compatible = "brcm,bcm6345-wdt";
			reg = <0x480 0x14>;
			clocks = <&wdt_clk>;
		};

		wdt2: watchdog@4c0 {
			compatible = "brcm,bcm6345-wdt";
			reg = <0x4c0 0x14>;
			clocks = <&wdt_clk>;
		};

		wdt-reboot {
			compatible = "wdt-reboot";
			wdt = <&wdt1>;
		};

		gpio0: gpio-controller@500 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x500 0x4>,
			      <0x520 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		gpio1: gpio-controller@504 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x504 0x4>,
			      <0x524 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		gpio2: gpio-controller@508 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x508 0x4>,
			      <0x528 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		gpio3: gpio-controller@50c {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x50c 0x4>,
			      <0x52c 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		gpio4: gpio-controller@510 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x510 0x4>,
			      <0x530 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		gpio5: gpio-controller@514 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x514 0x4>,
			      <0x534 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		gpio6: gpio-controller@518 {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x518 0x4>,
			      <0x538 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		gpio7: gpio-controller@51c {
			compatible = "brcm,bcm6345-gpio";
			reg = <0x51c 0x4>,
			      <0x53c 0x4>;
			gpio-controller;
			#gpio-cells = <2>;

			status = "disabled";
		};

		hsspi: spi-controller@1000 {
			compatible = "brcm,bcm6328-hsspi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1000 0x600>;
			clocks = <&hsspi_pll>, <&hsspi_pll>;
			clock-names = "hsspi", "pll";
			spi-max-frequency = <100000000>;
			num-cs = <8>;

			status = "disabled";
		};

		nand: nand-controller@1800 {
			compatible = "brcm,nand-bcm63158",
				     "brcm,brcmnand-v5.0",
				     "brcm,brcmnand";
			reg-names = "nand", "nand-int-base", "nand-cache";
			reg = <0x1800 0x180>,
			      <0x2000 0x10>,
			      <0x1c00 0x200>;
			parameter-page-big-endian = <0>;

			status = "disabled";
		};
	};
};