tree 6d1d7ebf6b8d33e2ba77c1928c6f71ffb7df7cab
parent a44ca1346dc7fdba4ae4f2906078f6b737c3f109
author Ludwig Zenz <lzenz@dh-electronics.de> 1555319588 +0200
committer Stefano Babic <sbabic@denx.de> 1556212584 +0200

ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration

The four x16 DDR3 are wired in T-topology. From NXP AN4467:
'Although not required, T-Topologies may also benefit from performing
Write Leveling as there are package delays on both the processor and DDR
devices that can be de-skewed by performing Write Leveling. Therefore,
Freescale recommends determining Write Leveling calibration parameters
for all boards, regardless of topology used.'
That is why write level calibration is also done.

Signed-off-by: Ludwig Zenz <lzenz@dh-electronics.com>