/*
 * Device Tree Source commonly used by UniPhier ARM SoCs
 *
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+	X11
 */

/include/ "skeleton.dtsi"

/ {
	clocks {
		refclk: ref {
			#clock-cells = <0>;
			compatible = "fixed-clock";
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&uart_clk>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&uart_clk>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&uart_clk>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&uart_clk>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
		};

		smpctrl@59800000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		mio: mioctrl@59810000 {
			/* specify compatible in each SoC DTSI */
			reg = <0x59810000 0x800>;
			#clock-cells = <1>;
		};

		peri: perictrl@59820000 {
			/* specify compatible in each SoC DTSI */
			reg = <0x59820000 0x200>;
			#clock-cells = <1>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0x104>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0x104>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		pinctrl: pinctrl@5f801000 {
			/* specify compatible in each SoC DTSI */
			reg = <0x5f801000 0xe00>;
		};

		sysctrl: sysctrl@61840000 {
			/* specify compatible in each SoC DTSI */
			reg = <0x61840000 0x4000>;
			#clock-cells = <1>;
			clock-names = "ref";
			clocks = <&refclk>;
		};

		nand: nand@68000000 {
			compatible = "denali,denali-nand-dt";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			reg-names = "nand_data", "denali_reg";
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"