tree c940f64052b4f2cc4872d6bac58e9bba74aa16d0
parent 5ce94c74a6b59922d4280573f2438e4f5f9b29a8
author Kever Yang <kever.yang@rock-chips.com> 1571796533 +0800
committer Kever Yang <kever.yang@rock-chips.com> 1573389620 +0800

rockchip: rk3328: defconfig: no need to reserve IRAM for SPL

We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.

Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.

The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>