tree 0790e0977f61242f1c686b58bc20e2a9dad0eaa4
parent 68620c9698f109c1f001f80d282138a5c67cabef
author Jagan Teki <jagan@amarulasolutions.com> 1551293819 +0530
committer Jagan Teki <jagan@amarulasolutions.com> 1552117595 +0530

clk: sunxi: h3: Implement EPHY CLK and RESET

EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>