tree 33e1f29fa3bcb8865a9b21926c8e0df7ffc71310
parent 5c564226fc8948e435edea8eb8c5c4afbc5edef1
author Andrew Bradford <andrew.bradford@kodakalaris.com> 1433349459 -0400
committer Simon Glass <sjg@chromium.org> 1433408598 -0600

x86: baytrail: pci region 3 is not always mapped to end of ram

Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up.  There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>