/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2022 MediaTek Inc. All rights reserved.
 *
 * Author: Weijie Gao <weijie.gao@mediatek.com>
 */

#ifndef _DT_BINDINGS_MT7621_CLK_H_
#define _DT_BINDINGS_MT7621_CLK_H_

#define MT7621_CLK_XTAL		0
#define MT7621_CLK_CPU		1
#define MT7621_CLK_BUS		2
#define MT7621_CLK_50M		3
#define MT7621_CLK_125M		4
#define MT7621_CLK_150M		5
#define MT7621_CLK_250M		6
#define MT7621_CLK_270M		7

#define MT7621_CLK_HSDMA	8
#define MT7621_CLK_FE		9
#define MT7621_CLK_SP_DIVTX	10
#define MT7621_CLK_TIMER	11
#define MT7621_CLK_PCM		12
#define MT7621_CLK_PIO		13
#define MT7621_CLK_GDMA		14
#define MT7621_CLK_NAND		15
#define MT7621_CLK_I2C		16
#define MT7621_CLK_I2S		17
#define MT7621_CLK_SPI		18
#define MT7621_CLK_UART1	19
#define MT7621_CLK_UART2	20
#define MT7621_CLK_UART3	21
#define MT7621_CLK_ETH		22
#define MT7621_CLK_PCIE0	23
#define MT7621_CLK_PCIE1	24
#define MT7621_CLK_PCIE2	25
#define MT7621_CLK_CRYPTO	26
#define MT7621_CLK_SHXC		27

#define MT7621_CLK_MAX		28

/* for u-boot only */
#define MT7621_CLK_DDR		29

#endif /* _DT_BINDINGS_MT7621_CLK_H_ */