tree 5cdcc92067973c361982d2c2d5ddbfa36ad43a74
parent 9b54b0e37b72aa9bfff09cbbe13465abfa143f84
author Marek Vasut <marex@denx.de> 1684360959 +0200
committer Patrice Chotard <patrice.chotard@foss.st.com> 1692191997 +0200

ARM: stm32: Power cycle Buck3 in reset on DHSOM

In case the DHSOM is in suspend state and either reset button is pushed
or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
as follows:

  "
  RAM: DDR3L 32bits 2x4Gb 533MHz
  DDR invalid size : 0x4, expected 0x40000000
  DRAM init failed: -22
  ### ERROR ### Please RESET the board ###
  "

Avoid this failure by not keeping any Buck regulators enabled during reset,
let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3
VDD enabled during reset is ST specific, move this addition to ST specific
SPL board initialization so that it wouldn't affect the DHSOM .

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>