tree 483c584aa38656dd0ac9a11ab7beffe8d886ee5f
parent f84880f0f31e2d293b987d37446dc8a2e34aa925
author Dave Gerlach <d-gerlach@ti.com> 1392726721 -0500
committer Tom Rini <trini@ti.com> 1393944127 -0500

ARM: AM43xx: Change DDR3 Reset Value

The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value
of the ddr reset value for DDR3 before the EMIF takes over. We must have
this bit set high so that on exit from DeepSleep0 within the kernel the
reset line has the proper value.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>