// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
 * Copyright : STMicroelectronics 2018
 */

/ {
	aliases {
		gpio0 = &gpioa;
		gpio1 = &gpiob;
		gpio2 = &gpioc;
		gpio3 = &gpiod;
		gpio4 = &gpioe;
		gpio5 = &gpiof;
		gpio6 = &gpiog;
		gpio7 = &gpioh;
		gpio8 = &gpioi;
		gpio9 = &gpioj;
		gpio10 = &gpiok;
		gpio25 = &gpioz;
		pinctrl0 = &pinctrl;
		pinctrl1 = &pinctrl_z;
	};

	clocks {
		u-boot,dm-pre-reloc;
	};

	/* need PSCI for sysreset during board_f */
	psci {
		u-boot,dm-pre-proper;
	};

	reboot {
		u-boot,dm-pre-reloc;
		compatible = "syscon-reboot";
		regmap = <&rcc>;
		offset = <0x404>;
		mask = <0x1>;
	};

	soc {
		u-boot,dm-pre-reloc;

		ddr: ddr@5a003000 {
			u-boot,dm-pre-reloc;

			compatible = "st,stm32mp1-ddr";

			reg = <0x5A003000 0x550
			       0x5A004000 0x234>;

			clocks = <&rcc AXIDCG>,
				 <&rcc DDRC1>,
				 <&rcc DDRC2>,
				 <&rcc DDRPHYC>,
				 <&rcc DDRCAPB>,
				 <&rcc DDRPHYCAPB>;

			clock-names = "axidcg",
				      "ddrc1",
				      "ddrc2",
				      "ddrphyc",
				      "ddrcapb",
				      "ddrphycapb";

			status = "okay";
		};
	};
};

&bsec {
	u-boot,dm-pre-reloc;
};

&clk_csi {
	u-boot,dm-pre-reloc;
};

&clk_hsi {
	u-boot,dm-pre-reloc;
};

&clk_hse {
	u-boot,dm-pre-reloc;
};

&clk_lsi {
	u-boot,dm-pre-reloc;
};

&clk_lse {
	u-boot,dm-pre-reloc;
};

&cpu0_opp_table {
	u-boot,dm-spl;
	opp-650000000 {
		u-boot,dm-spl;
	};
	opp-800000000 {
		u-boot,dm-spl;
	};
};

&gpioa {
	u-boot,dm-pre-reloc;
};

&gpiob {
	u-boot,dm-pre-reloc;
};

&gpioc {
	u-boot,dm-pre-reloc;
};

&gpiod {
	u-boot,dm-pre-reloc;
};

&gpioe {
	u-boot,dm-pre-reloc;
};

&gpiof {
	u-boot,dm-pre-reloc;
};

&gpiog {
	u-boot,dm-pre-reloc;
};

&gpioh {
	u-boot,dm-pre-reloc;
};

&gpioi {
	u-boot,dm-pre-reloc;
};

&gpioj {
	u-boot,dm-pre-reloc;
};

&gpiok {
	u-boot,dm-pre-reloc;
};

&gpioz {
	u-boot,dm-pre-reloc;
};

&iwdg2 {
	u-boot,dm-pre-reloc;
};

/* pre-reloc probe = reserve video frame buffer in video_reserve() */
&ltdc {
	u-boot,dm-pre-proper;
};

&pinctrl {
	u-boot,dm-pre-reloc;
};

&pinctrl_z {
	u-boot,dm-pre-reloc;
};

&pwr_regulators {
	u-boot,dm-pre-reloc;
};

&rcc {
	u-boot,dm-pre-reloc;
	#address-cells = <1>;
	#size-cells = <0>;
};

&sdmmc1 {
	compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};

&sdmmc2 {
	compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};

&sdmmc3 {
	compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};

&usart1 {
	resets = <&rcc USART1_R>;
};

&usart2 {
	resets = <&rcc USART2_R>;
};

&usart3 {
	resets = <&rcc USART3_R>;
};

&uart4 {
	resets = <&rcc UART4_R>;
};

&uart5 {
	resets = <&rcc UART5_R>;
};

&usart6 {
	resets = <&rcc USART6_R>;
};

&uart7 {
	resets = <&rcc UART7_R>;
};

&uart8{
	resets = <&rcc UART8_R>;
};

&usbotg_hs {
	compatible = "st,stm32mp1-hsotg", "snps,dwc2";
};