tree 138f8c0882a0d0dec188aa4ccf452d9cd82a72e2
parent fbcaa260e5cdaeb0cc153c823e034076ac6a6902
author Anup Patel <Anup.Patel@wdc.com> 1551082489 +0000
committer Andes <uboot@andestech.com> 1551229953 +0800

clk: Add SiFive FU540 PRCI clock driver

Add driver code for the SiFive FU540 PRCI IP block.  This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra <wesley@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>