tree 85ef8dec9348cc1e33f4cf0daa4082c0cae2520e
parent 0993fc026b5003cfc7da9abe8a3fddbd26c7ee44
author Bin Meng <bmeng.cn@gmail.com> 1442214461 -0700
committer Simon Glass <sjg@chromium.org> 1442454833 -0600

x86: quark: Configure MTRR to enable cache

Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
are accessed indirectly via the message port and not the traditional
MSR mechanism. Only UC, WT and WB cache types are supported.

We configure all the fixed range MTRRs with common values (VGA RAM
as UC, others as WB) and 3 variable range MTRRs for ROM/eSRAM/RAM as
WB, which significantly improves the boot time performance.

With this commit, it takes only 2 seconds for U-Boot to boot to shell
on Intel Galileo board. Previously it took about 6 seconds.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>