tree 4a31e92876cb55753ac16aac95fb2dbe57236b3d
parent 0298f4c0032e2ba7e417aacc66da98887a2e0a5b
author Masahiro Yamada <yamada.masahiro@socionext.com> 1474497739 +0900
committer Masahiro Yamada <yamada.masahiro@socionext.com> 1474560023 +0900

ARM: uniphier: add PLL init code for LD11 SoC

 - Initialize PLLs (SPL initializes only DPLL to save the precious
   SPL memory footprint)
 - Adjust CPLL/MPLL to the final tape-out frequency
 - Set the Cortex-A53 clock to the maximum frequency since it is
   running at 500MHz (SPLL/4) on startup

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>