tree aa26d3f7b56cae4b17e72784a4b790a1141acdf9
parent 0302a207c3129ff50c590fafe8bc46dfb4dbeac5
author Michal Simek <michal.simek@xilinx.com> 1648205407 +0100
committer Michal Simek <michal.simek@xilinx.com> 1648538399 +0200

serial: zynq: Change fifo behavior in debug mode

Serial IP has output buffer which status is indicated by two bits. If fifo
if empty or full. Default configuration is that chars are pushed to fifo
till it is full. Time to time it is visible that chars are scambled and
logs are not visible. Not sure what it is exactly happening but all the
time it helps to change driver behavior to write only one char at a time.
That's why enable this mode when debug uart is enabled not to see scrambled
chars in debug by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/332b2106d7a8190dd1001b5387f8bd1fba2e061b.1648205405.git.michal.simek@xilinx.com