tree 34dee6df0d4914e66bc0bc9a3c652b20fc0e7eb7
parent 965de8b91bddd1f5967240d1d44005719b09dd5e
author Lokesh Vutla <lokeshvutla@ti.com> 1386667942 +0530
committer Tom Rini <trini@ti.com> 1387419284 -0500

ARM: AM43xx: EPOS_EVM: Add support for LPDDR2

AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>