tree 0bc10413b7d7ef030566206bba5ff0df5b2046c6
parent 8b528709c5bba6a8d0ec83b20545bbd75f082704
author Shengzhou Liu <Shengzhou.Liu@nxp.com> 1462328421 +0800
committer York Sun <york.sun@nxp.com> 1464987995 -0700

drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl

The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>