tree 0908b429e67d6bdd3e5732b64a2be9e82b1de37a
parent b8f3ce013700893a3ed4ae280a2aec0ab95af3de
author Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 1580296110 +0300
committer Alexey Brodkin <abrodkin@synopsys.com> 1581529659 +0300

CLK: HSDK: fix HDMI clock calculation

HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>