// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2017 exceet electronics GmbH
 * Copyright (C) 2018 Kontron Electronics GmbH
 * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
 */

#include <dt-bindings/gpio/gpio.h>

/ {
	chosen {
		stdout-path = &uart4;
	};

	memory@80000000 {
		reg = <0x80000000 0x10000000>;
		device_type = "memory";
	};
};

&ecspi2 {
	cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2>;
	status = "okay";

	spi-flash@0 {
		compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy1: ethernet-phy@1 {
			reg = <1>;
			micrel,led-mode = <0>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";
		};
	};
};

&fec2 {
	phy-mode = "rmii";
	status = "disabled";
};

&qspi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_qspi>;
	status = "okay";

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-nand";
		spi-max-frequency = <104000000>;
		spi-tx-bus-width = <4>;
		spi-rx-bus-width = <4>;
		reg = <0>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_reset_out>;

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX6UL_PAD_CSI_DATA03__ECSPI2_MISO      0x100b1
			MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI      0x100b1
			MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK      0x100b1
			MX6UL_PAD_CSI_DATA01__GPIO4_IO22       0x100b1
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b009
		>;
	};

	pinctrl_enet1_mdio: enet1mdiogrp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
		>;
	};

	pinctrl_qspi: qspigrp {
		fsl,pins = <
			MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
			MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
			MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
			MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
			MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
			MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
		>;
	};

	pinctrl_reset_out: rstoutgrp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09      0x1b0b0
		>;
	};
};