tree c31439c473ea9fce54ff32851bf2d3058acab33a
parent 373b9003410b44a1133060c2e63483b278fb476b
author Rick Chen <rick@andestech.com> 1514267748 +0800
committer Tom Rini <trini@konsulko.com> 1515762312 -0500

riscv: cpu: Add nx25 to support RISC-V

Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch

Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.

Detail verification message please see doc/README.ae250.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Signed-off-by: Greentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>