tree 95e115e585b41b95a80b4f702ecf1be2d7619896
parent 1038e033e1e999b11568c8daf0a4e19b31086266
author Patrice Chotard <patrice.chotard@st.com> 1518106849 +0100
committer Tom Rini <trini@konsulko.com> 1520991937 -0400

clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock

Configure SAI PLL configuration to generate LTDC pixel clock on
the PLLSAIR output.

PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>