tree 06f65144c3f6c86b8a9618e0f3a09f18f30646eb
parent 2492ba8a3b005d8a541baa31b62293e02388405d
author John Keeping <john@metanate.com> 1673975267 +0000
committer Kever Yang <kever.yang@rock-chips.com> 1677578846 +0800

mmc: rockchip_dw_mmc: fix DDR52 8-bit mode handling

The RK3288 TRM states that, for 8-bit DDR modes:

	The CLKDIV register should always be programmed with a value
	higher than zero (0); that is, a clock divider should always be
	used for 8-bit DDR mode.

In Linux, the driver applies this logic for all SoCs using the driver
and does not distinguish RK3288, so presumably this requirement is the
same for all other Rockchip SoCs using this IP.

Add the necessary code to double the clock frequency when 8-bit DDR is
selected.  The dw_mmc core already handles setting CLKDIV correctly
given the input clock and desired bus clock.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>