tree 5e96a47140a0a142c05e936ffbb66f8ff0c31c8c
parent 5cb27c5d44ac789f0f0583b57c15dc708ca55c69
author York Sun <yorksun@freescale.com> 1409896363 +0800
committer York Sun <yorksun@freescale.com> 1410197434 -0700

driver/ddr/fsl: Add support of overriding chip select write leveling

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun <yorksun@freescale.com>