tree 61e6f45481b4efa6949c5456fe81dcf0135480e6
parent 123922b1e583dc6bd6b8909af2d788f6e40a33a9
author York Sun <yorksun@freescale.com> 1349682264 +0000
committer Andy Fleming <afleming@freescale.com> 1350934287 -0500

powerpc/mpc8xxx: Fix DDR initialization waiting for D_INIT

When ECC is enabled, DDR controller needs to initialize the data and ecc.
The wait time can be calcuated with total memory size, bus width, bus speed
and interleaving mode. If it went wrong, it is bettert to timeout than
waiting for D_INIT to clear, where it probably hangs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>