tree 2f0bdc934071e1d44c144745d9fb4f8948776c77
parent f1fd79afad97df76f0d84847d98d80d5a8c7e4ec
author Michal Simek <michal.simek@xilinx.com> 1612269202 +0100
committer Michal Simek <michal.simek@xilinx.com> 1612959627 +0100

xilinx: common: Fix CONFIG_XILINX_OF_BOARD_DTB_ADDR handling for ZynqMP

Fix bug introduced by commit listed below. It is for cases where Versal or
ZynqMP don't have DDR mapped. Later SPL was also excluded by
commit a672b9871b57 ("xilinx: common: Do not touch
CONFIG_XILINX_OF_BOARD_DTB_ADDR in SPL").

Fixes: 506009fc1022 ("xilinx: common: Change macro handling in board_fdt_blob_setup()")
Signed-off-by: Michal Simek <michal.simek@xilinx.com>