tree f3d40f8eb70814b549f5d445fb1f602d8d9e9744
parent 6bd13ee94ecf0e3124efdd51758df21db8100083
author Michal Simek <michal.simek@xilinx.com> 1543483862 +0100
committer Michal Simek <michal.simek@xilinx.com> 1543483862 +0100

ARM: zynq: Wire SPL configuration for cse nor/nand targets

These symlinks are here only for testing purpose where SPL is used
for soc configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>