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wdenkc00b5f82002-11-03 11:12:02 +00001/*----------------------------------------------------------------------------+
2|
wdenkba56f622004-02-06 23:19:44 +00003| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
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6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
wdenkc00b5f82002-11-03 11:12:02 +00009|
wdenkba56f622004-02-06 23:19:44 +000010| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
wdenkc00b5f82002-11-03 11:12:02 +000013|
wdenkba56f622004-02-06 23:19:44 +000014| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
wdenkc00b5f82002-11-03 11:12:02 +000017|
wdenkba56f622004-02-06 23:19:44 +000018| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
wdenkc00b5f82002-11-03 11:12:02 +000020+----------------------------------------------------------------------------*/
21
wdenkba56f622004-02-06 23:19:44 +000022#ifndef __PPC440_H__
wdenkc00b5f82002-11-03 11:12:02 +000023#define __PPC440_H__
24
25/*--------------------------------------------------------------------- */
26/* Special Purpose Registers */
27/*--------------------------------------------------------------------- */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020028#define xer_reg 0x001
29#define lr_reg 0x008
wdenkba56f622004-02-06 23:19:44 +000030#define dec 0x016 /* decrementer */
31#define srr0 0x01a /* save/restore register 0 */
32#define srr1 0x01b /* save/restore register 1 */
33#define pid 0x030 /* process id */
34#define decar 0x036 /* decrementer auto-reload */
35#define csrr0 0x03a /* critical save/restore register 0 */
36#define csrr1 0x03b /* critical save/restore register 1 */
37#define dear 0x03d /* data exception address register */
38#define esr 0x03e /* exception syndrome register */
39#define ivpr 0x03f /* interrupt prefix register */
40#define usprg0 0x100 /* user special purpose register general 0 */
41#define usprg1 0x110 /* user special purpose register general 1 */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +020042#define tblr 0x10c /* time base lower, read only */
43#define tbur 0x10d /* time base upper, read only */
wdenkba56f622004-02-06 23:19:44 +000044#define sprg1 0x111 /* special purpose register general 1 */
45#define sprg2 0x112 /* special purpose register general 2 */
46#define sprg3 0x113 /* special purpose register general 3 */
47#define sprg4 0x114 /* special purpose register general 4 */
48#define sprg5 0x115 /* special purpose register general 5 */
49#define sprg6 0x116 /* special purpose register general 6 */
50#define sprg7 0x117 /* special purpose register general 7 */
51#define tbl 0x11c /* time base lower (supervisor)*/
52#define tbu 0x11d /* time base upper (supervisor)*/
53#define pir 0x11e /* processor id register */
54/*#define pvr 0x11f processor version register */
55#define dbsr 0x130 /* debug status register */
56#define dbcr0 0x134 /* debug control register 0 */
57#define dbcr1 0x135 /* debug control register 1 */
58#define dbcr2 0x136 /* debug control register 2 */
59#define iac1 0x138 /* instruction address compare 1 */
60#define iac2 0x139 /* instruction address compare 2 */
61#define iac3 0x13a /* instruction address compare 3 */
62#define iac4 0x13b /* instruction address compare 4 */
63#define dac1 0x13c /* data address compare 1 */
64#define dac2 0x13d /* data address compare 2 */
65#define dvc1 0x13e /* data value compare 1 */
66#define dvc2 0x13f /* data value compare 2 */
67#define tsr 0x150 /* timer status register */
68#define tcr 0x154 /* timer control register */
69#define ivor0 0x190 /* interrupt vector offset register 0 */
70#define ivor1 0x191 /* interrupt vector offset register 1 */
71#define ivor2 0x192 /* interrupt vector offset register 2 */
72#define ivor3 0x193 /* interrupt vector offset register 3 */
73#define ivor4 0x194 /* interrupt vector offset register 4 */
74#define ivor5 0x195 /* interrupt vector offset register 5 */
75#define ivor6 0x196 /* interrupt vector offset register 6 */
76#define ivor7 0x197 /* interrupt vector offset register 7 */
77#define ivor8 0x198 /* interrupt vector offset register 8 */
78#define ivor9 0x199 /* interrupt vector offset register 9 */
79#define ivor10 0x19a /* interrupt vector offset register 10 */
80#define ivor11 0x19b /* interrupt vector offset register 11 */
81#define ivor12 0x19c /* interrupt vector offset register 12 */
82#define ivor13 0x19d /* interrupt vector offset register 13 */
83#define ivor14 0x19e /* interrupt vector offset register 14 */
84#define ivor15 0x19f /* interrupt vector offset register 15 */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020085#if defined(CONFIG_440)
wdenkba56f622004-02-06 23:19:44 +000086#define mcsrr0 0x23a /* machine check save/restore register 0 */
87#define mcsrr1 0x23b /* mahcine check save/restore register 1 */
88#define mcsr 0x23c /* machine check status register */
89#endif
90#define inv0 0x370 /* instruction cache normal victim 0 */
91#define inv1 0x371 /* instruction cache normal victim 1 */
92#define inv2 0x372 /* instruction cache normal victim 2 */
93#define inv3 0x373 /* instruction cache normal victim 3 */
94#define itv0 0x374 /* instruction cache transient victim 0 */
95#define itv1 0x375 /* instruction cache transient victim 1 */
96#define itv2 0x376 /* instruction cache transient victim 2 */
97#define itv3 0x377 /* instruction cache transient victim 3 */
98#define dnv0 0x390 /* data cache normal victim 0 */
99#define dnv1 0x391 /* data cache normal victim 1 */
100#define dnv2 0x392 /* data cache normal victim 2 */
101#define dnv3 0x393 /* data cache normal victim 3 */
102#define dtv0 0x394 /* data cache transient victim 0 */
103#define dtv1 0x395 /* data cache transient victim 1 */
104#define dtv2 0x396 /* data cache transient victim 2 */
105#define dtv3 0x397 /* data cache transient victim 3 */
106#define dvlim 0x398 /* data cache victim limit */
107#define ivlim 0x399 /* instruction cache victim limit */
108#define rstcfg 0x39b /* reset configuration */
109#define dcdbtrl 0x39c /* data cache debug tag register low */
110#define dcdbtrh 0x39d /* data cache debug tag register high */
111#define icdbtrl 0x39e /* instruction cache debug tag register low */
112#define icdbtrh 0x39f /* instruction cache debug tag register high */
113#define mmucr 0x3b2 /* mmu control register */
114#define ccr0 0x3b3 /* core configuration register 0 */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200115#define ccr1 0x378 /* core configuration for 440x5 only */
wdenkba56f622004-02-06 23:19:44 +0000116#define icdbdr 0x3d3 /* instruction cache debug data register */
117#define dbdr 0x3f3 /* debug data register */
wdenkc00b5f82002-11-03 11:12:02 +0000118
119/******************************************************************************
120 * DCRs & Related
121 ******************************************************************************/
122
123/*-----------------------------------------------------------------------------
wdenkba56f622004-02-06 23:19:44 +0000124 | Clocking Controller
125 +----------------------------------------------------------------------------*/
126#define CLOCKING_DCR_BASE 0x0c
127#define clkcfga (CLOCKING_DCR_BASE+0x0)
128#define clkcfgd (CLOCKING_DCR_BASE+0x1)
129
130/* values for clkcfga register - indirect addressing of these regs */
131#define clk_clkukpd 0x0020
132#define clk_pllc 0x0040
133#define clk_plld 0x0060
134#define clk_primad 0x0080
135#define clk_primbd 0x00a0
136#define clk_opbd 0x00c0
137#define clk_perd 0x00e0
138#define clk_mald 0x0100
Stefan Roesec157d8e2005-08-01 16:41:48 +0200139#define clk_spcid 0x0120
wdenkba56f622004-02-06 23:19:44 +0000140#define clk_icfg 0x0140
141
142/* 440gx sdr register definations */
143#define SDR_DCR_BASE 0x0e
144#define sdrcfga (SDR_DCR_BASE+0x0)
145#define sdrcfgd (SDR_DCR_BASE+0x1)
146#define sdr_sdstp0 0x0020 /* */
147#define sdr_sdstp1 0x0021 /* */
Stefan Roese90e6f412007-04-18 12:05:59 +0200148#define SDR_PINSTP 0x0040
wdenkba56f622004-02-06 23:19:44 +0000149#define sdr_sdcs 0x0060
150#define sdr_ecid0 0x0080
151#define sdr_ecid1 0x0081
152#define sdr_ecid2 0x0082
153#define sdr_jtag 0x00c0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200154#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
wdenkba56f622004-02-06 23:19:44 +0000155#define sdr_ddrdl 0x00e0
Stefan Roese887e2ec2006-09-07 11:51:23 +0200156#else
157#define sdr_cfg 0x00e0
158#define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
159#define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
160#define SDR_CFG_32BITS 0x00000000 /* 32 bits */
161#define SDR_CFG_64BITS 0x01000000 /* 64 bits */
162#define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
163#define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
164#define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
165#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
wdenkba56f622004-02-06 23:19:44 +0000166#define sdr_ebc 0x0100
167#define sdr_uart0 0x0120 /* UART0 Config */
168#define sdr_uart1 0x0121 /* UART1 Config */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200169#define sdr_uart2 0x0122 /* UART2 Config */
170#define sdr_uart3 0x0123 /* UART3 Config */
wdenkba56f622004-02-06 23:19:44 +0000171#define sdr_cp440 0x0180
172#define sdr_xcr 0x01c0
173#define sdr_xpllc 0x01c1
174#define sdr_xplld 0x01c2
175#define sdr_srst 0x0200
176#define sdr_slpipe 0x0220
Stefan Roesec157d8e2005-08-01 16:41:48 +0200177#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
178#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
wdenkba56f622004-02-06 23:19:44 +0000179#define sdr_mirq0 0x0260
180#define sdr_mirq1 0x0261
181#define sdr_maltbl 0x0280
182#define sdr_malrbl 0x02a0
183#define sdr_maltbs 0x02c0
184#define sdr_malrbs 0x02e0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200185#define sdr_pci0 0x0300
186#define sdr_usb0 0x0320
wdenkba56f622004-02-06 23:19:44 +0000187#define sdr_cust0 0x4000
wdenkba56f622004-02-06 23:19:44 +0000188#define sdr_cust1 0x4002
wdenkba56f622004-02-06 23:19:44 +0000189#define sdr_pfc0 0x4100 /* Pin Function 0 */
190#define sdr_pfc1 0x4101 /* Pin Function 1 */
191#define sdr_plbtr 0x4200
192#define sdr_mfr 0x4300 /* SDR0_MFR reg */
193
Stefan Roese887e2ec2006-09-07 11:51:23 +0200194#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */
195#define DDR0_00 0x00
196#define DDR0_01 0x01
197#define DDR0_02 0x02
198#define DDR0_03 0x03
199#define DDR0_04 0x04
200#define DDR0_05 0x05
201#define DDR0_06 0x06
202#define DDR0_07 0x07
203#define DDR0_08 0x08
204#define DDR0_09 0x09
205#define DDR0_10 0x0A
206#define DDR0_11 0x0B
207#define DDR0_12 0x0C
208#define DDR0_13 0x0D
209#define DDR0_14 0x0E
210#define DDR0_15 0x0F
211#define DDR0_16 0x10
212#define DDR0_17 0x11
213#define DDR0_18 0x12
214#define DDR0_19 0x13
215#define DDR0_20 0x14
216#define DDR0_21 0x15
217#define DDR0_22 0x16
218#define DDR0_23 0x17
219#define DDR0_24 0x18
220#define DDR0_25 0x19
221#define DDR0_26 0x1A
222#define DDR0_27 0x1B
223#define DDR0_28 0x1C
224#define DDR0_29 0x1D
225#define DDR0_30 0x1E
226#define DDR0_31 0x1F
227#define DDR0_32 0x20
228#define DDR0_33 0x21
229#define DDR0_34 0x22
230#define DDR0_35 0x23
231#define DDR0_36 0x24
232#define DDR0_37 0x25
233#define DDR0_38 0x26
234#define DDR0_39 0x27
235#define DDR0_40 0x28
236#define DDR0_41 0x29
237#define DDR0_42 0x2A
238#define DDR0_43 0x2B
239#define DDR0_44 0x2C
240#endif /*CONFIG_440EPX*/
241
wdenkba56f622004-02-06 23:19:44 +0000242/*-----------------------------------------------------------------------------
wdenkc00b5f82002-11-03 11:12:02 +0000243 | SDRAM Controller
244 +----------------------------------------------------------------------------*/
245#define SDRAM_DCR_BASE 0x10
wdenkba56f622004-02-06 23:19:44 +0000246#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */
247#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */
wdenkc00b5f82002-11-03 11:12:02 +0000248
wdenkba56f622004-02-06 23:19:44 +0000249/* values for memcfga register - indirect addressing of these regs */
250#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
251#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
252#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
253#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
254#define mem_bear 0x0010 /* bus error address reg */
255#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
256#define mem_mirq_set 0x0012 /* bus master interrupt (set) */
257#define mem_slio 0x0018 /* ddr sdram slave interface options */
258#define mem_cfg0 0x0020 /* ddr sdram options 0 */
259#define mem_cfg1 0x0021 /* ddr sdram options 1 */
260#define mem_devopt 0x0022 /* ddr sdram device options */
261#define mem_mcsts 0x0024 /* memory controller status */
262#define mem_rtr 0x0030 /* refresh timer register */
263#define mem_pmit 0x0034 /* power management idle timer */
264#define mem_uabba 0x0038 /* plb UABus base address */
265#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
266#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
267#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
268#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
269#define mem_tr0 0x0080 /* sdram timing register 0 */
270#define mem_tr1 0x0081 /* sdram timing register 1 */
271#define mem_clktr 0x0082 /* ddr clock timing register */
272#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
273#define mem_dlycal 0x0084 /* delay line calibration register */
274#define mem_eccesr 0x0098 /* ECC error status */
wdenkc00b5f82002-11-03 11:12:02 +0000275
Marian Balakowiczbba68372006-06-30 18:35:04 +0200276#ifdef CONFIG_440GX
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200277#define sdr_amp 0x0240
278#define sdr_xpllc 0x01c1
279#define sdr_xplld 0x01c2
280#define sdr_xcr 0x01c0
281#define sdr_sdstp2 0x4001
282#define sdr_sdstp3 0x4003
Marian Balakowiczbba68372006-06-30 18:35:04 +0200283#endif /* CONFIG_440GX */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200284
285#ifdef CONFIG_440SPE
286#undef sdr_sdstp2
287#define sdr_sdstp2 0x0022
288#undef sdr_sdstp3
289#define sdr_sdstp3 0x0023
290#define sdr_ddr0 0x00E1
291#define sdr_uart2 0x0122
292#define sdr_xcr0 0x01c0
293/* #define sdr_xcr1 0x01c3 only one PCIX - SG */
294/* #define sdr_xcr2 0x01c6 only one PCIX - SG */
295#define sdr_xpllc0 0x01c1
296#define sdr_xplld0 0x01c2
297#define sdr_xpllc1 0x01c4 /*notRCW - SG */
298#define sdr_xplld1 0x01c5 /*notRCW - SG */
299#define sdr_xpllc2 0x01c7 /*notRCW - SG */
300#define sdr_xplld2 0x01c8 /*notRCW - SG */
301#define sdr_amp0 0x0240
302#define sdr_amp1 0x0241
303#define sdr_cust2 0x4004
304#define sdr_cust3 0x4006
305#define sdr_sdstp4 0x4001
306#define sdr_sdstp5 0x4003
307#define sdr_sdstp6 0x4005
308#define sdr_sdstp7 0x4007
309
310/*----------------------------------------------------------------------------+
311| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
312+----------------------------------------------------------------------------*/
313#define CCR0_PRE 0x40000000
314#define CCR0_CRPE 0x08000000
315#define CCR0_DSTG 0x00200000
316#define CCR0_DAPUIB 0x00100000
317#define CCR0_DTB 0x00008000
318#define CCR0_GICBT 0x00004000
319#define CCR0_GDCBT 0x00002000
320#define CCR0_FLSTA 0x00000100
321#define CCR0_ICSLC_MASK 0x0000000C
322#define CCR0_ICSLT_MASK 0x00000003
323#define CCR1_TCS_MASK 0x00000080
324#define CCR1_TCS_INTCLK 0x00000000
325#define CCR1_TCS_EXTCLK 0x00000080
326#define MMUCR_SEOA 0x01000000
327#define MMUCR_U1TE 0x00400000
328#define MMUCR_U2SWOAE 0x00200000
329#define MMUCR_DULXE 0x00800000
330#define MMUCR_IULXE 0x00400000
331#define MMUCR_STS 0x00100000
332#define MMUCR_STID_MASK 0x000000FF
333
334#define SDR0_CFGADDR 0x00E
335#define SDR0_CFGDATA 0x00F
336
337/******************************************************************************
338 * PCI express defines
339 ******************************************************************************/
340#define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
341#define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
342#define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
343#define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
344#define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
345#define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
346#define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
347#define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
348#define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
349#define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
350#define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
351#define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
352#define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
353#define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
354#define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
355#define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
356#define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
357#define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
358#define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
359#define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
360#define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
361#define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
362#define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
363#define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
364#define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
365#define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
366#define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
367#define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
368#define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
369#define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
370#define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
371#define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
372#define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
373
374#define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
375#define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
376#define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
377#define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
378#define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
379#define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
380#define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
381#define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
382#define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
383#define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
384#define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
385#define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
386#define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
387#define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
388#define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
389#define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
390#define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
391#define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
392#define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
393#define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
394#define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
395#define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
396#define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
397#define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
398#define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
399#define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
400#define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
401#define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
402#define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
403#define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
404#define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
405#define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
406#define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
407#define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
408#define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
409#define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
410#define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
411#define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
412#define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
413#define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
414#define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
415#define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
416#define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
Stefan Roesedf294492007-03-08 10:06:09 +0100417#endif /* CONFIG_440SPE */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200418
Stefan Roesedf294492007-03-08 10:06:09 +0100419#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200420/*----------------------------------------------------------------------------+
421| SDRAM Controller
422+----------------------------------------------------------------------------*/
423/*-----------------------------------------------------------------------------+
424| SDRAM DLYCAL Options
425+-----------------------------------------------------------------------------*/
426#define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
427#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
428#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
429
430/*----------------------------------------------------------------------------+
431| Memory queue defines
432+----------------------------------------------------------------------------*/
433/* A REVOIR versus RWC - SG*/
434#define SDRAMQ_DCR_BASE 0x040
435
436#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
437#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
438#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
439#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
440#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
441#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
442#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
443#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
444#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
445#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
446#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
447#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
448#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
449#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
450#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
451
452/*-----------------------------------------------------------------------------+
453| Memory Bank 0-7 configuration
454+-----------------------------------------------------------------------------*/
Stefan Roesedf294492007-03-08 10:06:09 +0100455#if defined(CONFIG_440SPE)
456#define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200457#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
458#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
Stefan Roesedf294492007-03-08 10:06:09 +0100459#endif /* CONFIG_440SPE */
460#if defined(CONFIG_440SP)
461#define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
462#define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000))
463#define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000))
464#endif /* CONFIG_440SP */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200465#define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
466#define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
467#define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
468#define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
469#define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
470#define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
471#define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
472#define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
473#define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
474#define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
475#define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
476#define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
477#define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
478#define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
479
480/*----------------------------------------------------------------------------+
481| Memory controller defines
482+----------------------------------------------------------------------------*/
483#define SDRAMC_DCR_BASE 0x010
484#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */
485#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */
486
487/* A REVOIR versus specs 4 bank - SG*/
488#define SDRAM_MCSTAT 0x14 /* memory controller status */
489#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
490#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
491#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
492#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
493#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
494#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
495#define SDRAM_CODT 0x26 /* on die termination for controller */
496#define SDRAM_VVPR 0x27 /* variable VRef programmming */
497#define SDRAM_OPARS 0x28 /* on chip driver control setup */
498#define SDRAM_OPART 0x29 /* on chip driver control trigger */
499#define SDRAM_RTR 0x30 /* refresh timer */
500#define SDRAM_PMIT 0x34 /* power management idle timer */
501#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
502#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
503#define SDRAM_MB2CF 0x48
504#define SDRAM_MB3CF 0x4C
505#define SDRAM_INITPLR0 0x50 /* manual initialization control */
506#define SDRAM_INITPLR1 0x51 /* manual initialization control */
507#define SDRAM_INITPLR2 0x52 /* manual initialization control */
508#define SDRAM_INITPLR3 0x53 /* manual initialization control */
509#define SDRAM_INITPLR4 0x54 /* manual initialization control */
510#define SDRAM_INITPLR5 0x55 /* manual initialization control */
511#define SDRAM_INITPLR6 0x56 /* manual initialization control */
512#define SDRAM_INITPLR7 0x57 /* manual initialization control */
513#define SDRAM_INITPLR8 0x58 /* manual initialization control */
514#define SDRAM_INITPLR9 0x59 /* manual initialization control */
515#define SDRAM_INITPLR10 0x5a /* manual initialization control */
516#define SDRAM_INITPLR11 0x5b /* manual initialization control */
517#define SDRAM_INITPLR12 0x5c /* manual initialization control */
518#define SDRAM_INITPLR13 0x5d /* manual initialization control */
519#define SDRAM_INITPLR14 0x5e /* manual initialization control */
520#define SDRAM_INITPLR15 0x5f /* manual initialization control */
521#define SDRAM_RQDC 0x70 /* read DQS delay control */
522#define SDRAM_RFDC 0x74 /* read feedback delay control */
523#define SDRAM_RDCC 0x78 /* read data capture control */
524#define SDRAM_DLCR 0x7A /* delay line calibration */
525#define SDRAM_CLKTR 0x80 /* DDR clock timing */
526#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
527#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
528#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
529#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
530#define SDRAM_MMODE 0x88 /* memory mode */
531#define SDRAM_MEMODE 0x89 /* memory extended mode */
532#define SDRAM_ECCCR 0x98 /* ECC error status */
533#define SDRAM_CID 0xA4 /* core ID */
534#define SDRAM_RID 0xA8 /* revision ID */
535
536/*-----------------------------------------------------------------------------+
537| Memory Controller Status
538+-----------------------------------------------------------------------------*/
539#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
540#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
541#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
Stefan Roese4745aca2007-02-20 10:57:08 +0100542#define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200543#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
Stefan Roese4745aca2007-02-20 10:57:08 +0100544#define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
545#define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
546#define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
547#define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200548
549/*-----------------------------------------------------------------------------+
550| Memory Controller Options 1
551+-----------------------------------------------------------------------------*/
552#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
553#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
554#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
555#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
556#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
557#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
558#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
559#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
560#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
561#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
562#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
563#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
564#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
565#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
566#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
567#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
568#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
569#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
570#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
571#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
572#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
573#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
574#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
575#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
576#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
577#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
578#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
579#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
580#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
581#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
582#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
583#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
584#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
585#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
586#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
587
588/*-----------------------------------------------------------------------------+
589| Memory Controller Options 2
590+-----------------------------------------------------------------------------*/
591#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
592#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
593#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
594#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
595#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
596#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
597#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
598#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
599#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
600#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
601#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
602#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
603#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
604#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
605#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
606#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
607#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
608#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
609
610/*-----------------------------------------------------------------------------+
611| SDRAM Refresh Timer Register
612+-----------------------------------------------------------------------------*/
613#define SDRAM_RTR_RINT_MASK 0xFFF80000
614#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
615#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
616
617/*-----------------------------------------------------------------------------+
618| SDRAM Read DQS Delay Control Register
619+-----------------------------------------------------------------------------*/
620#define SDRAM_RQDC_RQDE_MASK 0x80000000
621#define SDRAM_RQDC_RQDE_DISABLE 0x00000000
622#define SDRAM_RQDC_RQDE_ENABLE 0x80000000
623#define SDRAM_RQDC_RQFD_MASK 0x000001FF
624#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
625
626#define SDRAM_RQDC_RQFD_MAX 0x1FF
627
628/*-----------------------------------------------------------------------------+
629| SDRAM Read Data Capture Control Register
630+-----------------------------------------------------------------------------*/
631#define SDRAM_RDCC_RDSS_MASK 0xC0000000
632#define SDRAM_RDCC_RDSS_T1 0x00000000
633#define SDRAM_RDCC_RDSS_T2 0x40000000
634#define SDRAM_RDCC_RDSS_T3 0x80000000
635#define SDRAM_RDCC_RDSS_T4 0xC0000000
636#define SDRAM_RDCC_RSAE_MASK 0x00000001
637#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
638#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
639
640/*-----------------------------------------------------------------------------+
641| SDRAM Read Feedback Delay Control Register
642+-----------------------------------------------------------------------------*/
643#define SDRAM_RFDC_ARSE_MASK 0x80000000
644#define SDRAM_RFDC_ARSE_DISABLE 0x80000000
645#define SDRAM_RFDC_ARSE_ENABLE 0x00000000
646#define SDRAM_RFDC_RFOS_MASK 0x007F0000
647#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
648#define SDRAM_RFDC_RFFD_MASK 0x000003FF
649#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
650
651#define SDRAM_RFDC_RFFD_MAX 0x7FF
652
653/*-----------------------------------------------------------------------------+
654| SDRAM Delay Line Calibration Register
655+-----------------------------------------------------------------------------*/
656#define SDRAM_DLCR_DCLM_MASK 0x80000000
657#define SDRAM_DLCR_DCLM_MANUEL 0x80000000
658#define SDRAM_DLCR_DCLM_AUTO 0x00000000
659#define SDRAM_DLCR_DLCR_MASK 0x08000000
660#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
661#define SDRAM_DLCR_DLCR_IDLE 0x00000000
662#define SDRAM_DLCR_DLCS_MASK 0x07000000
663#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
664#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
665#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
666#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
667#define SDRAM_DLCR_DLCS_ERROR 0x04000000
668#define SDRAM_DLCR_DLCV_MASK 0x000001FF
669#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
670#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
671
672/*-----------------------------------------------------------------------------+
673| SDRAM Controller On Die Termination Register
674+-----------------------------------------------------------------------------*/
675#define SDRAM_CODT_ODT_ON 0x80000000
676#define SDRAM_CODT_ODT_OFF 0x00000000
677#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
678#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
679#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
680#define SDRAM_CODT_DQS_MASK 0x00000010
681#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
682#define SDRAM_CODT_DQS_SINGLE_END 0x00000010
683#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
684#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
685#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
686#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
687#define SDRAM_CODT_IO_HIZ 0x00000000
688#define SDRAM_CODT_IO_NMODE 0x00000001
689
690/*-----------------------------------------------------------------------------+
691| SDRAM Mode Register
692+-----------------------------------------------------------------------------*/
693#define SDRAM_MMODE_WR_MASK 0x00000E00
694#define SDRAM_MMODE_WR_DDR1 0x00000000
695#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
696#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
697#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
698#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
699#define SDRAM_MMODE_DCL_MASK 0x00000070
700#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
701#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
702#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
703#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
704#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
705#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
706#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
707#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
708#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
709
710/*-----------------------------------------------------------------------------+
711| SDRAM Extended Mode Register
712+-----------------------------------------------------------------------------*/
713#define SDRAM_MEMODE_DIC_MASK 0x00000002
714#define SDRAM_MEMODE_DIC_NORMAL 0x00000000
715#define SDRAM_MEMODE_DIC_WEAK 0x00000002
716#define SDRAM_MEMODE_DLL_MASK 0x00000001
717#define SDRAM_MEMODE_DLL_DISABLE 0x00000001
718#define SDRAM_MEMODE_DLL_ENABLE 0x00000000
719#define SDRAM_MEMODE_RTT_MASK 0x00000044
720#define SDRAM_MEMODE_RTT_DISABLED 0x00000000
721#define SDRAM_MEMODE_RTT_75OHM 0x00000004
722#define SDRAM_MEMODE_RTT_150OHM 0x00000040
723#define SDRAM_MEMODE_DQS_MASK 0x00000400
724#define SDRAM_MEMODE_DQS_DISABLE 0x00000400
725#define SDRAM_MEMODE_DQS_ENABLE 0x00000000
726
727/*-----------------------------------------------------------------------------+
728| SDRAM Clock Timing Register
729+-----------------------------------------------------------------------------*/
730#define SDRAM_CLKTR_CLKP_MASK 0xC0000000
731#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
732#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
733
734/*-----------------------------------------------------------------------------+
735| SDRAM Write Timing Register
736+-----------------------------------------------------------------------------*/
737#define SDRAM_WRDTR_LLWP_MASK 0x10000000
738#define SDRAM_WRDTR_LLWP_DIS 0x10000000
739#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
740#define SDRAM_WRDTR_WTR_MASK 0x0E000000
741#define SDRAM_WRDTR_WTR_0_DEG 0x06000000
Stefan Roese4745aca2007-02-20 10:57:08 +0100742#define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200743#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
744#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
745
746/*-----------------------------------------------------------------------------+
747| SDRAM SDTR1 Options
748+-----------------------------------------------------------------------------*/
749#define SDRAM_SDTR1_LDOF_MASK 0x80000000
750#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
751#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
752#define SDRAM_SDTR1_RTW_MASK 0x00F00000
753#define SDRAM_SDTR1_RTW_2_CLK 0x00200000
754#define SDRAM_SDTR1_RTW_3_CLK 0x00300000
755#define SDRAM_SDTR1_WTWO_MASK 0x000F0000
756#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
757#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
758#define SDRAM_SDTR1_RTRO_MASK 0x0000F000
759#define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
760#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
761
762/*-----------------------------------------------------------------------------+
763| SDRAM SDTR2 Options
764+-----------------------------------------------------------------------------*/
765#define SDRAM_SDTR2_RCD_MASK 0xF0000000
766#define SDRAM_SDTR2_RCD_1_CLK 0x10000000
767#define SDRAM_SDTR2_RCD_2_CLK 0x20000000
768#define SDRAM_SDTR2_RCD_3_CLK 0x30000000
769#define SDRAM_SDTR2_RCD_4_CLK 0x40000000
770#define SDRAM_SDTR2_RCD_5_CLK 0x50000000
771#define SDRAM_SDTR2_WTR_MASK 0x0F000000
772#define SDRAM_SDTR2_WTR_1_CLK 0x01000000
773#define SDRAM_SDTR2_WTR_2_CLK 0x02000000
774#define SDRAM_SDTR2_WTR_3_CLK 0x03000000
775#define SDRAM_SDTR2_WTR_4_CLK 0x04000000
776#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
777#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
778#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
779#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
780#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
781#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
782#define SDRAM_SDTR2_WPC_MASK 0x0000F000
783#define SDRAM_SDTR2_WPC_2_CLK 0x00002000
784#define SDRAM_SDTR2_WPC_3_CLK 0x00003000
785#define SDRAM_SDTR2_WPC_4_CLK 0x00004000
786#define SDRAM_SDTR2_WPC_5_CLK 0x00005000
787#define SDRAM_SDTR2_WPC_6_CLK 0x00006000
788#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
789#define SDRAM_SDTR2_RPC_MASK 0x00000F00
790#define SDRAM_SDTR2_RPC_2_CLK 0x00000200
791#define SDRAM_SDTR2_RPC_3_CLK 0x00000300
792#define SDRAM_SDTR2_RPC_4_CLK 0x00000400
793#define SDRAM_SDTR2_RP_MASK 0x000000F0
794#define SDRAM_SDTR2_RP_3_CLK 0x00000030
795#define SDRAM_SDTR2_RP_4_CLK 0x00000040
796#define SDRAM_SDTR2_RP_5_CLK 0x00000050
797#define SDRAM_SDTR2_RP_6_CLK 0x00000060
798#define SDRAM_SDTR2_RP_7_CLK 0x00000070
799#define SDRAM_SDTR2_RRD_MASK 0x0000000F
800#define SDRAM_SDTR2_RRD_2_CLK 0x00000002
801#define SDRAM_SDTR2_RRD_3_CLK 0x00000003
802
803/*-----------------------------------------------------------------------------+
804| SDRAM SDTR3 Options
805+-----------------------------------------------------------------------------*/
806#define SDRAM_SDTR3_RAS_MASK 0x1F000000
807#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
808#define SDRAM_SDTR3_RC_MASK 0x001F0000
809#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
810#define SDRAM_SDTR3_XCS_MASK 0x00001F00
811#define SDRAM_SDTR3_XCS 0x00000D00
812#define SDRAM_SDTR3_RFC_MASK 0x0000003F
813#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
814
815/*-----------------------------------------------------------------------------+
816| Memory Bank 0-1 configuration
817+-----------------------------------------------------------------------------*/
818#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
819#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
820#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
821#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
822#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
823#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
824#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
825#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
826#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
827#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
828#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
829#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
830#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
831#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
832#endif /* CONFIG_440SPE */
833
wdenkc00b5f82002-11-03 11:12:02 +0000834/*-----------------------------------------------------------------------------
Wolfgang Denk6ed6ce62005-09-25 16:01:42 +0200835 | External Bus Controller
wdenkc00b5f82002-11-03 11:12:02 +0000836 +----------------------------------------------------------------------------*/
837#define EBC_DCR_BASE 0x12
838#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */
839#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */
wdenkba56f622004-02-06 23:19:44 +0000840/* values for ebccfga register - indirect addressing of these regs */
841#define pb0cr 0x00 /* periph bank 0 config reg */
842#define pb1cr 0x01 /* periph bank 1 config reg */
843#define pb2cr 0x02 /* periph bank 2 config reg */
844#define pb3cr 0x03 /* periph bank 3 config reg */
845#define pb4cr 0x04 /* periph bank 4 config reg */
846#define pb5cr 0x05 /* periph bank 5 config reg */
847#define pb6cr 0x06 /* periph bank 6 config reg */
848#define pb7cr 0x07 /* periph bank 7 config reg */
849#define pb0ap 0x10 /* periph bank 0 access parameters */
850#define pb1ap 0x11 /* periph bank 1 access parameters */
851#define pb2ap 0x12 /* periph bank 2 access parameters */
852#define pb3ap 0x13 /* periph bank 3 access parameters */
853#define pb4ap 0x14 /* periph bank 4 access parameters */
854#define pb5ap 0x15 /* periph bank 5 access parameters */
855#define pb6ap 0x16 /* periph bank 6 access parameters */
856#define pb7ap 0x17 /* periph bank 7 access parameters */
857#define pbear 0x20 /* periph bus error addr reg */
858#define pbesr 0x21 /* periph bus error status reg */
859#define xbcfg 0x23 /* external bus configuration reg */
Stefan Roese4745aca2007-02-20 10:57:08 +0100860#define EBC0_CFG 0x23 /* external bus configuration reg */
Wolfgang Denk6ed6ce62005-09-25 16:01:42 +0200861#define xbcid 0x24 /* external bus core id reg */
wdenkc00b5f82002-11-03 11:12:02 +0000862
Stefan Roese887e2ec2006-09-07 11:51:23 +0200863#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
864 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200865
866/* PLB4 to PLB3 Bridge OUT */
867#define P4P3_DCR_BASE 0x020
868#define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
869#define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
870#define p4p3_eadr (P4P3_DCR_BASE+0x2)
871#define p4p3_euadr (P4P3_DCR_BASE+0x3)
872#define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
873#define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
874#define p4p3_confg (P4P3_DCR_BASE+0x6)
875#define p4p3_pic (P4P3_DCR_BASE+0x7)
876#define p4p3_peir (P4P3_DCR_BASE+0x8)
877#define p4p3_rev (P4P3_DCR_BASE+0xA)
878
879/* PLB3 to PLB4 Bridge IN */
880#define P3P4_DCR_BASE 0x030
881#define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
882#define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
883#define p3p4_eadr (P3P4_DCR_BASE+0x2)
884#define p3p4_euadr (P3P4_DCR_BASE+0x3)
885#define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
886#define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
887#define p3p4_confg (P3P4_DCR_BASE+0x6)
888#define p3p4_pic (P3P4_DCR_BASE+0x7)
889#define p3p4_peir (P3P4_DCR_BASE+0x8)
890#define p3p4_rev (P3P4_DCR_BASE+0xA)
891
892/* PLB3 Arbiter */
893#define PLB3_DCR_BASE 0x070
894#define plb3_revid (PLB3_DCR_BASE+0x2)
895#define plb3_besr (PLB3_DCR_BASE+0x3)
896#define plb3_bear (PLB3_DCR_BASE+0x6)
897#define plb3_acr (PLB3_DCR_BASE+0x7)
898
899/* PLB4 Arbiter - PowerPC440EP Pass1 */
900#define PLB4_DCR_BASE 0x080
Stefan Roesea78bc442007-01-05 10:40:36 +0100901#define plb4_acr (PLB4_DCR_BASE+0x1)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200902#define plb4_revid (PLB4_DCR_BASE+0x2)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200903#define plb4_besr (PLB4_DCR_BASE+0x4)
904#define plb4_bearl (PLB4_DCR_BASE+0x6)
905#define plb4_bearh (PLB4_DCR_BASE+0x7)
906
Stefan Roesea78bc442007-01-05 10:40:36 +0100907#define PLB4_ACR_WRP (0x80000000 >> 7)
908
Stefan Roesec157d8e2005-08-01 16:41:48 +0200909/* Nebula PLB4 Arbiter - PowerPC440EP */
910#define PLB_ARBITER_BASE 0x80
911
912#define plb0_revid (PLB_ARBITER_BASE+ 0x00)
913#define plb0_acr (PLB_ARBITER_BASE+ 0x01)
914#define plb0_acr_ppm_mask 0xF0000000
915#define plb0_acr_ppm_fixed 0x00000000
916#define plb0_acr_ppm_fair 0xD0000000
917#define plb0_acr_hbu_mask 0x08000000
918#define plb0_acr_hbu_disabled 0x00000000
919#define plb0_acr_hbu_enabled 0x08000000
920#define plb0_acr_rdp_mask 0x06000000
921#define plb0_acr_rdp_disabled 0x00000000
922#define plb0_acr_rdp_2deep 0x02000000
923#define plb0_acr_rdp_3deep 0x04000000
924#define plb0_acr_rdp_4deep 0x06000000
925#define plb0_acr_wrp_mask 0x01000000
926#define plb0_acr_wrp_disabled 0x00000000
927#define plb0_acr_wrp_2deep 0x01000000
928
929#define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
930#define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
931#define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
932#define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
933#define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
934
935#define plb1_acr (PLB_ARBITER_BASE+ 0x09)
936#define plb1_acr_ppm_mask 0xF0000000
937#define plb1_acr_ppm_fixed 0x00000000
938#define plb1_acr_ppm_fair 0xD0000000
939#define plb1_acr_hbu_mask 0x08000000
940#define plb1_acr_hbu_disabled 0x00000000
941#define plb1_acr_hbu_enabled 0x08000000
942#define plb1_acr_rdp_mask 0x06000000
943#define plb1_acr_rdp_disabled 0x00000000
944#define plb1_acr_rdp_2deep 0x02000000
945#define plb1_acr_rdp_3deep 0x04000000
946#define plb1_acr_rdp_4deep 0x06000000
947#define plb1_acr_wrp_mask 0x01000000
948#define plb1_acr_wrp_disabled 0x00000000
949#define plb1_acr_wrp_2deep 0x01000000
950
951#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
952#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
953#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
954#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
955
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200956#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
957 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese17f50f222005-08-04 17:09:16 +0200958/* Pin Function Control Register 1 */
959#define SDR0_PFC1 0x4101
960#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
961#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
962#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
963#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
964#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
965#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
966#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
967#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
968#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
969#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
970#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
971#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
972#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
973#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
974#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
975#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
976#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
977#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
978#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
979#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
980#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
981#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
982#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
983#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
984
985#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
986#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
987#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
988#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
989
990/* USB Control Register */
991#define SDR0_USB0 0x0320
992#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
993#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
994#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
995#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
996#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
997#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
998
Stefan Roese887e2ec2006-09-07 11:51:23 +0200999/* Miscealleneaous Function Reg. */
1000#define SDR0_MFR 0x4300
1001#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
1002#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
1003#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
1004#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
1005#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1006#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1007#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1008#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1009#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1010#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1011#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1012#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1013#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
1014
1015#define SDR0_MFR_ERRATA3_EN0 0x00800000
1016#define SDR0_MFR_ERRATA3_EN1 0x00400000
1017#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
1018#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1019#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
1020#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
1021#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
1022
1023#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
1024
1025#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1026#define SDR_USB2D0CR 0x0320
1027#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
1028#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
1029#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
1030
1031#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
1032#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
1033#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
1034
1035#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
1036#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
1037#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
1038
1039/* USB2 Host Control Register */
1040#define SDR0_USB2H0CR 0x0340
1041#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
1042#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
1043#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
1044#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
1045
1046/* Pin Function Control Register 1 */
1047#define SDR0_PFC1 0x4101
1048#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1049#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1050#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1051
1052#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
1053#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
1054#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
1055#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
1056#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
1057#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
1058#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
1059#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
1060
1061#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1062#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1063#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1064#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1065#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
1066#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
1067#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1068#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1069#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1070#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
1071#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
1072#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
1073#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
1074#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
1075#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
1076#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1077#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
1078#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
1079#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
1080#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
1081#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
1082
1083#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
1084#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
1085#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
1086#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
1087
1088/* Ethernet PLL Configuration Register */
1089#define SDR0_PFC2 0x4102
1090#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
1091#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
1092#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
1093#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
1094
1095#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
1096#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
1097#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
1098#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
1099#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
1100#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
1101#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
1102#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
1103
Stefan Roeseb765ffb2007-06-15 08:18:01 +02001104#define SDR0_PFC4 0x4104
1105
Stefan Roese887e2ec2006-09-07 11:51:23 +02001106/* USB2PHY0 Control Register */
1107#define SDR0_USB2PHY0CR 0x4103
1108#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
1109#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
1110#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
1111
1112#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
1113#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
1114#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
1115
1116#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
1117#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
1118#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
1119
1120#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
1121#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
1122#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
1123
1124#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
1125#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
1126#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
1127
1128#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
1129#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
1130#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
1131
1132#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
1133#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
1134#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
1135
1136#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
1137#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
1138#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
1139
1140#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
1141#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
1142#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
1143
1144#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
1145#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
1146#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
1147#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
1148
1149/* Miscealleneaous Function Reg. */
1150#define SDR0_MFR 0x4300
1151#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
1152#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
1153#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
1154#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
1155#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1156#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1157#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1158#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1159#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1160#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1161#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
1162
1163#define SDR0_MFR_ERRATA3_EN0 0x00800000
1164#define SDR0_MFR_ERRATA3_EN1 0x00400000
1165#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
1166#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1167#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
1168#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
1169#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
1170
1171#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
1172
Stefan Roese17f50f222005-08-04 17:09:16 +02001173/* CUST0 Customer Configuration Register0 */
1174#define SDR0_CUST0 0x4000
1175#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
1176#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
1177#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
1178#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
1179
1180#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
1181#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
1182#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
1183
1184#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
1185#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
1186#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
1187
1188#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
1189#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
1190#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1191
1192#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
1193#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
1194#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1195
1196#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
1197#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
1198#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
1199
1200#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
1201#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
1202#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
1203
1204#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
1205#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
1206#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
1207
1208#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
1209#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
1210#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
1211#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
1212#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
1213#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
1214#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
1215
1216/* CUST1 Customer Configuration Register1 */
1217#define SDR0_CUST1 0x4002
1218#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
1219#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
1220#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
1221
1222/* Pin Function Control Register 0 */
1223#define SDR0_PFC0 0x4100
1224#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
1225#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
1226#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
1227#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1228#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
1229
1230/* Pin Function Control Register 1 */
1231#define SDR0_PFC1 0x4101
1232#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1233#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1234#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1235#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1236#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1237#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1238#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1239#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
1240#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
1241#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1242#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1243#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1244#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
1245#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
1246#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
1247#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
1248#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
1249#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
1250#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1251#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
1252#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
1253#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
1254#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
1255#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
1256
1257#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
1258#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
1259#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
1260#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
1261
Stefan Roese887e2ec2006-09-07 11:51:23 +02001262/*-----------------------------------------------------------------------------
1263 | Internal SRAM
1264 +----------------------------------------------------------------------------*/
1265#define ISRAM0_DCR_BASE 0x380
1266#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
1267#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
1268#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
1269#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
1270#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
1271#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
1272#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
1273#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
Stefan Roese17f50f222005-08-04 17:09:16 +02001274
Stefan Roesec157d8e2005-08-01 16:41:48 +02001275#else
1276
wdenkc00b5f82002-11-03 11:12:02 +00001277/*-----------------------------------------------------------------------------
1278 | Internal SRAM
1279 +----------------------------------------------------------------------------*/
1280#define ISRAM0_DCR_BASE 0x020
wdenkba56f622004-02-06 23:19:44 +00001281#define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
1282#define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
1283#define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
1284#define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
1285#define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
1286#define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
1287#define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
1288#define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
1289#define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
1290#define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
1291#define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
1292
1293/*-----------------------------------------------------------------------------
1294 | L2 Cache
1295 +----------------------------------------------------------------------------*/
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001296#if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
wdenkba56f622004-02-06 23:19:44 +00001297#define L2_CACHE_BASE 0x030
1298#define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
1299#define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
1300#define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
1301#define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
1302#define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
1303#define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
1304#define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
1305#define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
1306
Stefan Roese846b0dd2005-08-08 12:42:22 +02001307#endif /* CONFIG_440GX */
1308#endif /* !CONFIG_440EP !CONFIG_440GR*/
wdenkc00b5f82002-11-03 11:12:02 +00001309
1310/*-----------------------------------------------------------------------------
1311 | On-Chip Buses
1312 +----------------------------------------------------------------------------*/
1313/* TODO: as needed */
1314
1315/*-----------------------------------------------------------------------------
1316 | Clocking, Power Management and Chip Control
1317 +----------------------------------------------------------------------------*/
1318#define CNTRL_DCR_BASE 0x0b0
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001319#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
wdenk63153492005-04-03 20:55:38 +00001320#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
1321#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
1322#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
wdenkba56f622004-02-06 23:19:44 +00001323#else
wdenk63153492005-04-03 20:55:38 +00001324#define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
1325#define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
1326#define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
wdenkba56f622004-02-06 23:19:44 +00001327#endif
wdenkc00b5f82002-11-03 11:12:02 +00001328
wdenk63153492005-04-03 20:55:38 +00001329#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
1330#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
1331#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
1332#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
wdenkc00b5f82002-11-03 11:12:02 +00001333
1334#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
1335#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
1336#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
1337#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
1338
Stefan Roese5568e612005-11-22 13:20:42 +01001339#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
1340
wdenk63153492005-04-03 20:55:38 +00001341#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
1342#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
wdenkc00b5f82002-11-03 11:12:02 +00001343
1344/*-----------------------------------------------------------------------------
1345 | Universal interrupt controller
1346 +----------------------------------------------------------------------------*/
1347#define UIC0_DCR_BASE 0xc0
wdenkba56f622004-02-06 23:19:44 +00001348#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
1349#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
1350#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
1351#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
1352#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
1353#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
1354#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
1355#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
wdenkc00b5f82002-11-03 11:12:02 +00001356
1357#define UIC1_DCR_BASE 0xd0
wdenkba56f622004-02-06 23:19:44 +00001358#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
1359#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
1360#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
1361#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
1362#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
1363#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
1364#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
1365#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
1366
Stefan Roese887e2ec2006-09-07 11:51:23 +02001367#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001368#define UIC2_DCR_BASE 0xe0
Stefan Roese4e26f102006-11-29 12:03:57 +01001369#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
1370#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
1371#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
1372#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
1373#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
1374#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
1375#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
1376#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
1377#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001378
1379#define UIC3_DCR_BASE 0xf0
Stefan Roese4e26f102006-11-29 12:03:57 +01001380#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
1381#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
1382#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
1383#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
1384#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
1385#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
1386#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
1387#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
1388#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001389#endif /* CONFIG_440SPE */
1390
Stefan Roese846b0dd2005-08-08 12:42:22 +02001391#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001392#define UIC2_DCR_BASE 0x210
1393#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
1394#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
1395#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
1396#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
1397#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
1398#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
1399#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
1400#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
1401
1402
1403#define UIC_DCR_BASE 0x200
1404#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
1405#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
1406#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
1407#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
1408#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
1409#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
1410#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
1411#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
Stefan Roese846b0dd2005-08-08 12:42:22 +02001412#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +00001413
1414/* The following is for compatibility with 405 code */
1415#define uicsr uic0sr
1416#define uicer uic0er
1417#define uiccr uic0cr
1418#define uicpr uic0pr
1419#define uictr uic0tr
1420#define uicmsr uic0msr
1421#define uicvr uic0vr
1422#define uicvcr uic0vcr
1423
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001424#if defined(CONFIG_440SPE)
1425/*----------------------------------------------------------------------------+
1426| Clock / Power-on-reset DCR's.
1427+----------------------------------------------------------------------------*/
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001428#define CPR0_CLKUPD 0x20
1429#define CPR0_CLKUPD_BSY_MASK 0x80000000
1430#define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
1431#define CPR0_CLKUPD_BSY_BUSY 0x80000000
1432#define CPR0_CLKUPD_CUI_MASK 0x80000000
1433#define CPR0_CLKUPD_CUI_DISABLE 0x00000000
1434#define CPR0_CLKUPD_CUI_ENABLE 0x80000000
1435#define CPR0_CLKUPD_CUD_MASK 0x40000000
1436#define CPR0_CLKUPD_CUD_DISABLE 0x00000000
1437#define CPR0_CLKUPD_CUD_ENABLE 0x40000000
1438
1439#define CPR0_PLLC 0x40
1440#define CPR0_PLLC_RST_MASK 0x80000000
1441#define CPR0_PLLC_RST_PLLLOCKED 0x00000000
1442#define CPR0_PLLC_RST_PLLRESET 0x80000000
1443#define CPR0_PLLC_ENG_MASK 0x40000000
1444#define CPR0_PLLC_ENG_DISABLE 0x00000000
1445#define CPR0_PLLC_ENG_ENABLE 0x40000000
1446#define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1447#define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1448#define CPR0_PLLC_SRC_MASK 0x20000000
1449#define CPR0_PLLC_SRC_PLLOUTA 0x00000000
1450#define CPR0_PLLC_SRC_PLLOUTB 0x20000000
1451#define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1452#define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1453#define CPR0_PLLC_SEL_MASK 0x07000000
1454#define CPR0_PLLC_SEL_PLLOUT 0x00000000
1455#define CPR0_PLLC_SEL_CPU 0x01000000
1456#define CPR0_PLLC_SEL_EBC 0x05000000
1457#define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1458#define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
1459#define CPR0_PLLC_TUNE_MASK 0x000003FF
1460#define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
1461#define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
1462
1463#define CPR0_PLLD 0x60
1464#define CPR0_PLLD_FBDV_MASK 0x1F000000
1465#define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
1466#define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
1467#define CPR0_PLLD_FWDVA_MASK 0x000F0000
1468#define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
1469#define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
1470#define CPR0_PLLD_FWDVB_MASK 0x00000700
1471#define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
1472#define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
1473#define CPR0_PLLD_LFBDV_MASK 0x0000003F
1474#define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1475#define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1476
1477#define CPR0_PRIMAD 0x80
1478#define CPR0_PRIMAD_PRADV0_MASK 0x07000000
1479#define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1480#define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1481
1482#define CPR0_PRIMBD 0xA0
1483#define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
1484#define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1485#define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1486
1487#define CPR0_OPBD 0xC0
1488#define CPR0_OPBD_OPBDV0_MASK 0x03000000
1489#define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1490#define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1491
1492#define CPR0_PERD 0xE0
1493#define CPR0_PERD_PERDV0_MASK 0x03000000
1494#define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1495#define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1496
1497#define CPR0_MALD 0x100
1498#define CPR0_MALD_MALDV0_MASK 0x03000000
1499#define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1500#define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1501
1502#define CPR0_ICFG 0x140
1503#define CPR0_ICFG_RLI_MASK 0x80000000
1504#define CPR0_ICFG_RLI_RESETCPR 0x00000000
1505#define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
1506#define CPR0_ICFG_ICS_MASK 0x00000007
1507#define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1508#define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1509
1510/************************/
1511/* IIC defines */
1512/************************/
1513#define IIC0_MMIO_BASE 0xA0000400
1514#define IIC1_MMIO_BASE 0xA0000500
1515
1516#endif /* CONFIG_440SP */
1517
wdenkc00b5f82002-11-03 11:12:02 +00001518/*-----------------------------------------------------------------------------
1519 | DMA
1520 +----------------------------------------------------------------------------*/
1521#define DMA_DCR_BASE 0x100
wdenkba56f622004-02-06 23:19:44 +00001522#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
1523#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
1524#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
1525#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
1526#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
1527#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
wdenkc00b5f82002-11-03 11:12:02 +00001528#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
1529#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
wdenkba56f622004-02-06 23:19:44 +00001530#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
1531#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
1532#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
1533#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
1534#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
1535#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
wdenkc00b5f82002-11-03 11:12:02 +00001536#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
1537#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
wdenkba56f622004-02-06 23:19:44 +00001538#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
1539#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
1540#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
1541#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
1542#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
1543#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +00001544#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
1545#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
wdenkba56f622004-02-06 23:19:44 +00001546#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
1547#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
1548#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
1549#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
1550#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
1551#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
wdenkc00b5f82002-11-03 11:12:02 +00001552#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
1553#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
wdenkba56f622004-02-06 23:19:44 +00001554#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
1555#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
1556#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
1557#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
wdenkc00b5f82002-11-03 11:12:02 +00001558
1559/*-----------------------------------------------------------------------------
1560 | Memory Access Layer
1561 +----------------------------------------------------------------------------*/
1562#define MAL_DCR_BASE 0x180
wdenkba56f622004-02-06 23:19:44 +00001563#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
1564#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
1565#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
1566#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
1567#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +00001568#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
1569#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
wdenkba56f622004-02-06 23:19:44 +00001570#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
1571#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
1572#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
1573#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
wdenkc00b5f82002-11-03 11:12:02 +00001574#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
1575#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
wdenkba56f622004-02-06 23:19:44 +00001576#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
1577#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
1578#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
wdenkc00b5f82002-11-03 11:12:02 +00001579#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
1580#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
wdenkba56f622004-02-06 23:19:44 +00001581#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
1582#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
wdenkc00b5f82002-11-03 11:12:02 +00001583#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
1584#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
Stefan Roese846b0dd2005-08-08 12:42:22 +02001585#if defined(CONFIG_440GX)
Wolfgang Denkac611702006-09-20 23:47:49 +02001586#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
1587#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
Stefan Roese846b0dd2005-08-08 12:42:22 +02001588#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +00001589#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1590#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
Stefan Roese846b0dd2005-08-08 12:42:22 +02001591#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001592#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
1593#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
Stefan Roese846b0dd2005-08-08 12:42:22 +02001594#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +00001595
wdenkc00b5f82002-11-03 11:12:02 +00001596
1597/*---------------------------------------------------------------------------+
1598| Universal interrupt controller 0 interrupts (UIC0)
1599+---------------------------------------------------------------------------*/
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001600#if defined(CONFIG_440SP)
1601#define UIC_U0 0x80000000 /* UART 0 */
1602#define UIC_U1 0x40000000 /* UART 1 */
1603#define UIC_IIC0 0x20000000 /* IIC */
1604#define UIC_IIC1 0x10000000 /* IIC */
1605#define UIC_PIM 0x08000000 /* PCI0 inbound message */
1606#define UIC_PCRW 0x04000000 /* PCI0 command write register */
1607#define UIC_PPM 0x02000000 /* PCI0 power management */
1608#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
1609#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
1610#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
1611#define UIC_P1CRW 0x00200000 /* PCI1 command write register */
1612#define UIC_P1PM 0x00100000 /* PCI1 power management */
1613#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
1614#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
1615#define UIC_P2IM 0x00020000 /* PCI2 inbound message */
1616#define UIC_P2CRW 0x00010000 /* PCI2 command register write */
1617#define UIC_P2PM 0x00008000 /* PCI2 power management */
1618#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
1619#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
1620#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
1621#define UIC_D0CSF 0x00000800 /* DMA0 command status */
1622#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
1623#define UIC_D1CSF 0x00000200 /* DMA1 command status */
1624#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
1625#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
1626#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
1627#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
1628#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
1629#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
1630#define UIC_GPTCT 0x00000004 /* GPT count timer */
1631#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1632#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001633#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
wdenkba56f622004-02-06 23:19:44 +00001634#define UIC_U0 0x80000000 /* UART 0 */
1635#define UIC_U1 0x40000000 /* UART 1 */
1636#define UIC_IIC0 0x20000000 /* IIC */
1637#define UIC_IIC1 0x10000000 /* IIC */
1638#define UIC_PIM 0x08000000 /* PCI inbound message */
1639#define UIC_PCRW 0x04000000 /* PCI command register write */
1640#define UIC_PPM 0x02000000 /* PCI power management */
1641#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
1642#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1643#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1644#define UIC_MTE 0x00200000 /* MAL TXEOB */
1645#define UIC_MRE 0x00100000 /* MAL RXEOB */
1646#define UIC_D0 0x00080000 /* DMA channel 0 */
1647#define UIC_D1 0x00040000 /* DMA channel 1 */
1648#define UIC_D2 0x00020000 /* DMA channel 2 */
1649#define UIC_D3 0x00010000 /* DMA channel 3 */
1650#define UIC_RSVD0 0x00008000 /* Reserved */
1651#define UIC_RSVD1 0x00004000 /* Reserved */
1652#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
1653#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
1654#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
1655#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
1656#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
1657#define UIC_EIR0 0x00000100 /* External interrupt 0 */
1658#define UIC_EIR1 0x00000080 /* External interrupt 1 */
1659#define UIC_EIR2 0x00000040 /* External interrupt 2 */
1660#define UIC_EIR3 0x00000020 /* External interrupt 3 */
1661#define UIC_EIR4 0x00000010 /* External interrupt 4 */
1662#define UIC_EIR5 0x00000008 /* External interrupt 5 */
1663#define UIC_EIR6 0x00000004 /* External interrupt 6 */
1664#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1665#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001666
1667#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1668
1669#define UIC_U0 0x80000000 /* UART 0 */
1670#define UIC_U1 0x40000000 /* UART 1 */
1671#define UIC_IIC0 0x20000000 /* IIC */
1672#define UIC_KRD 0x10000000 /* Kasumi Ready for data */
1673#define UIC_KDA 0x08000000 /* Kasumi Data Available */
1674#define UIC_PCRW 0x04000000 /* PCI command register write */
1675#define UIC_PPM 0x02000000 /* PCI power management */
1676#define UIC_IIC1 0x01000000 /* IIC */
1677#define UIC_SPI 0x00800000 /* SPI */
1678#define UIC_EPCISER 0x00400000 /* External PCI SERR */
1679#define UIC_MTE 0x00200000 /* MAL TXEOB */
1680#define UIC_MRE 0x00100000 /* MAL RXEOB */
1681#define UIC_D0 0x00080000 /* DMA channel 0 */
1682#define UIC_D1 0x00040000 /* DMA channel 1 */
1683#define UIC_D2 0x00020000 /* DMA channel 2 */
1684#define UIC_D3 0x00010000 /* DMA channel 3 */
1685#define UIC_UD0 0x00008000 /* UDMA irq 0 */
1686#define UIC_UD1 0x00004000 /* UDMA irq 1 */
1687#define UIC_UD2 0x00002000 /* UDMA irq 2 */
1688#define UIC_UD3 0x00001000 /* UDMA irq 3 */
1689#define UIC_HSB2D 0x00000800 /* USB2.0 Device */
1690#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */
1691#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */
1692#define UIC_EIP94 0x00000100 /* Security EIP94 */
1693#define UIC_ETH0 0x00000080 /* Emac 0 */
1694#define UIC_ETH1 0x00000040 /* Emac 1 */
1695#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */
1696#define UIC_EIR4 0x00000010 /* External interrupt 4 */
1697#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */
1698#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */
1699#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1700#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1701
1702/* For compatibility with 405 code */
1703#define UIC_MAL_TXEOB UIC_MTE
1704#define UIC_MAL_RXEOB UIC_MRE
1705
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001706#elif !defined(CONFIG_440SPE)
1707#define UIC_U0 0x80000000 /* UART 0 */
1708#define UIC_U1 0x40000000 /* UART 1 */
1709#define UIC_IIC0 0x20000000 /* IIC */
1710#define UIC_IIC1 0x10000000 /* IIC */
1711#define UIC_PIM 0x08000000 /* PCI inbound message */
1712#define UIC_PCRW 0x04000000 /* PCI command register write */
1713#define UIC_PPM 0x02000000 /* PCI power management */
1714#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
1715#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1716#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1717#define UIC_MTE 0x00200000 /* MAL TXEOB */
1718#define UIC_MRE 0x00100000 /* MAL RXEOB */
1719#define UIC_D0 0x00080000 /* DMA channel 0 */
1720#define UIC_D1 0x00040000 /* DMA channel 1 */
1721#define UIC_D2 0x00020000 /* DMA channel 2 */
1722#define UIC_D3 0x00010000 /* DMA channel 3 */
1723#define UIC_RSVD0 0x00008000 /* Reserved */
1724#define UIC_RSVD1 0x00004000 /* Reserved */
1725#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
1726#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
1727#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
1728#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
1729#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
1730#define UIC_EIR0 0x00000100 /* External interrupt 0 */
1731#define UIC_EIR1 0x00000080 /* External interrupt 1 */
1732#define UIC_EIR2 0x00000040 /* External interrupt 2 */
1733#define UIC_EIR3 0x00000020 /* External interrupt 3 */
1734#define UIC_EIR4 0x00000010 /* External interrupt 4 */
1735#define UIC_EIR5 0x00000008 /* External interrupt 5 */
1736#define UIC_EIR6 0x00000004 /* External interrupt 6 */
1737#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1738#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1739#endif /* CONFIG_440GX */
wdenkc00b5f82002-11-03 11:12:02 +00001740
1741/* For compatibility with 405 code */
wdenkba56f622004-02-06 23:19:44 +00001742#define UIC_MAL_TXEOB UIC_MTE
1743#define UIC_MAL_RXEOB UIC_MRE
wdenkc00b5f82002-11-03 11:12:02 +00001744
1745/*---------------------------------------------------------------------------+
1746| Universal interrupt controller 1 interrupts (UIC1)
1747+---------------------------------------------------------------------------*/
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001748#if defined(CONFIG_440SP)
1749#define UIC_EIR0 0x80000000 /* External interrupt 0 */
1750#define UIC_MS 0x40000000 /* MAL SERR */
1751#define UIC_MTDE 0x20000000 /* MAL TXDE */
1752#define UIC_MRDE 0x10000000 /* MAL RXDE */
1753#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1754#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1755#define UIC_MTE 0x02000000 /* MAL TXEOB */
1756#define UIC_MRE 0x01000000 /* MAL RXEOB */
1757#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
1758#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
1759#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
1760#define UIC_L2C 0x00100000 /* L2 cache */
1761#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
1762#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
1763#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
1764#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
1765#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
1766#define UIC_EIR1 0x00004000 /* External interrupt 1 */
1767#define UIC_EIR2 0x00002000 /* External interrupt 2 */
1768#define UIC_EIR3 0x00001000 /* External interrupt 3 */
1769#define UIC_EIR4 0x00000800 /* External interrupt 4 */
1770#define UIC_EIR5 0x00000400 /* External interrupt 5 */
1771#define UIC_DMAE 0x00000200 /* DMA error */
1772#define UIC_I2OE 0x00000100 /* I2O error */
1773#define UIC_SRE 0x00000080 /* Serial ROM error */
1774#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
1775#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
1776#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
1777#define UIC_ETH0 0x00000008 /* Ethernet 0 */
1778#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1779#define UIC_ETH1 0x00000002 /* Reserved */
1780#define UIC_XOR 0x00000001 /* XOR */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001781#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
1782#define UIC_MS 0x80000000 /* MAL SERR */
1783#define UIC_MTDE 0x40000000 /* MAL TXDE */
1784#define UIC_MRDE 0x20000000 /* MAL RXDE */
1785#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
1786#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1787#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1788#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
1789#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
1790#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
1791#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
1792#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
1793#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
1794#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
1795#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
1796#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
1797#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
1798#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
1799#define UIC_PPMI 0x00004000 /* PPM interrupt status */
1800#define UIC_EIR7 0x00002000 /* External interrupt 7 */
1801#define UIC_EIR8 0x00001000 /* External interrupt 8 */
1802#define UIC_EIR9 0x00000800 /* External interrupt 9 */
1803#define UIC_EIR10 0x00000400 /* External interrupt 10 */
1804#define UIC_EIR11 0x00000200 /* External interrupt 11 */
1805#define UIC_EIR12 0x00000100 /* External interrupt 12 */
1806#define UIC_SRE 0x00000080 /* Serial ROM error */
1807#define UIC_RSVD2 0x00000040 /* Reserved */
1808#define UIC_RSVD3 0x00000020 /* Reserved */
1809#define UIC_PAE 0x00000010 /* PCI asynchronous error */
1810#define UIC_ETH0 0x00000008 /* Ethernet 0 */
1811#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1812#define UIC_ETH1 0x00000002 /* Ethernet 1 */
1813#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001814
1815#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1816
1817#define UIC_MS 0x80000000 /* MAL SERR */
1818#define UIC_MTDE 0x40000000 /* MAL TXDE */
1819#define UIC_MRDE 0x20000000 /* MAL RXDE */
1820#define UIC_U2 0x10000000 /* UART 2 */
1821#define UIC_U3 0x08000000 /* UART 3 */
1822#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1823#define UIC_NDFC 0x02000000 /* NDFC */
1824#define UIC_KSLE 0x01000000 /* KASUMI slave error */
1825#define UIC_CT5 0x00800000 /* GPT compare timer 5 */
1826#define UIC_CT6 0x00400000 /* GPT compare timer 6 */
1827#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */
1828#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */
1829#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */
1830#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */
1831#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */
1832#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */
1833#define UIC_CT0 0x00008000 /* GPT compare timer 0 */
1834#define UIC_CT1 0x00004000 /* GPT compare timer 1 */
1835#define UIC_EIR7 0x00002000 /* External interrupt 7 */
1836#define UIC_EIR8 0x00001000 /* External interrupt 8 */
1837#define UIC_EIR9 0x00000800 /* External interrupt 9 */
1838#define UIC_CT2 0x00000400 /* GPT compare timer 2 */
1839#define UIC_CT3 0x00000200 /* GPT compare timer 3 */
1840#define UIC_CT4 0x00000100 /* GPT compare timer 4 */
1841#define UIC_SRE 0x00000080 /* Serial ROM error */
1842#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */
1843#define UIC_RSVD0 0x00000020 /* Reserved */
1844#define UIC_EPCIPER 0x00000010 /* External PCI PERR */
1845#define UIC_EIR0 0x00000008 /* External interrupt 0 */
1846#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1847#define UIC_EIR1 0x00000002 /* External interrupt 1 */
1848#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1849
1850/* For compatibility with 405 code */
1851#define UIC_MAL_SERR UIC_MS
1852#define UIC_MAL_TXDE UIC_MTDE
1853#define UIC_MAL_RXDE UIC_MRDE
1854#define UIC_ENET UIC_ETH0
1855
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001856#elif !defined(CONFIG_440SPE)
wdenkba56f622004-02-06 23:19:44 +00001857#define UIC_MS 0x80000000 /* MAL SERR */
1858#define UIC_MTDE 0x40000000 /* MAL TXDE */
1859#define UIC_MRDE 0x20000000 /* MAL RXDE */
1860#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
1861#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1862#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1863#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
1864#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
1865#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
1866#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
1867#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
1868#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
1869#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
1870#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
1871#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
1872#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
1873#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
1874#define UIC_PPMI 0x00004000 /* PPM interrupt status */
1875#define UIC_EIR7 0x00002000 /* External interrupt 7 */
1876#define UIC_EIR8 0x00001000 /* External interrupt 8 */
1877#define UIC_EIR9 0x00000800 /* External interrupt 9 */
1878#define UIC_EIR10 0x00000400 /* External interrupt 10 */
1879#define UIC_EIR11 0x00000200 /* External interrupt 11 */
1880#define UIC_EIR12 0x00000100 /* External interrupt 12 */
1881#define UIC_SRE 0x00000080 /* Serial ROM error */
1882#define UIC_RSVD2 0x00000040 /* Reserved */
1883#define UIC_RSVD3 0x00000020 /* Reserved */
1884#define UIC_PAE 0x00000010 /* PCI asynchronous error */
1885#define UIC_ETH0 0x00000008 /* Ethernet 0 */
1886#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1887#define UIC_ETH1 0x00000002 /* Ethernet 1 */
1888#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001889#endif /* CONFIG_440SP */
wdenkc00b5f82002-11-03 11:12:02 +00001890
1891/* For compatibility with 405 code */
wdenkba56f622004-02-06 23:19:44 +00001892#define UIC_MAL_SERR UIC_MS
1893#define UIC_MAL_TXDE UIC_MTDE
1894#define UIC_MAL_RXDE UIC_MRDE
1895#define UIC_ENET UIC_ETH0
1896
1897/*---------------------------------------------------------------------------+
1898| Universal interrupt controller 2 interrupts (UIC2)
1899+---------------------------------------------------------------------------*/
Stefan Roese846b0dd2005-08-08 12:42:22 +02001900#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001901#define UIC_ETH2 0x80000000 /* Ethernet 2 */
1902#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
1903#define UIC_ETH3 0x20000000 /* Ethernet 3 */
1904#define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
1905#define UIC_TAH0 0x08000000 /* TAH 0 */
1906#define UIC_TAH1 0x04000000 /* TAH 1 */
1907#define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
1908#define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
1909#define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
1910#define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
1911#define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
1912#define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
1913#define UIC_IMUTO 0x00080000 /* IMU timeout */
1914#define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
1915#define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
1916#define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
1917#define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
1918#define UIC_EIR13 0x00004000 /* External interrupt 13 */
1919#define UIC_EIR14 0x00002000 /* External interrupt 14 */
1920#define UIC_EIR15 0x00001000 /* External interrupt 15 */
1921#define UIC_EIR16 0x00000800 /* External interrupt 16 */
1922#define UIC_EIR17 0x00000400 /* External interrupt 17 */
1923#define UIC_PCIVPD 0x00000200 /* PCI VPD */
1924#define UIC_L2C 0x00000100 /* L2 Cache */
1925#define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
1926#define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
1927#define UIC_RSVD26 0x00000020 /* Reserved */
1928#define UIC_RSVD27 0x00000010 /* Reserved */
1929#define UIC_RSVD28 0x00000008 /* Reserved */
1930#define UIC_RSVD29 0x00000004 /* Reserved */
1931#define UIC_RSVD30 0x00000002 /* Reserved */
1932#define UIC_RSVD31 0x00000001 /* Reserved */
Stefan Roese887e2ec2006-09-07 11:51:23 +02001933
1934#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
1935
1936#define UIC_EIR5 0x80000000 /* External interrupt 5 */
1937#define UIC_EIR6 0x40000000 /* External interrupt 6 */
1938#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */
1939#define UIC_EIR2 0x10000000 /* External interrupt 2 */
1940#define UIC_EIR3 0x08000000 /* External interrupt 3 */
1941#define UIC_DDR2 0x04000000 /* DDR2 sdram */
1942#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */
1943#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */
1944#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */
1945#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */
1946
Stefan Roese846b0dd2005-08-08 12:42:22 +02001947#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +00001948
1949/*---------------------------------------------------------------------------+
1950| Universal interrupt controller Base 0 interrupts (UICB0)
1951+---------------------------------------------------------------------------*/
Stefan Roese846b0dd2005-08-08 12:42:22 +02001952#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +00001953#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
1954#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
1955#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
1956#define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
1957#define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
1958#define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
1959
1960#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
1961 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
Stefan Roese887e2ec2006-09-07 11:51:23 +02001962
1963#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1964
1965#define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */
1966#define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */
1967#define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */
1968#define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */
1969
1970#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
1971 UICB0_UIC1CI | UICB0_UIC2NCI)
1972
Marian Balakowiczbba68372006-06-30 18:35:04 +02001973#endif /* CONFIG_440GX */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02001974/*---------------------------------------------------------------------------+
1975| Universal interrupt controller interrupts
1976+---------------------------------------------------------------------------*/
1977#if defined(CONFIG_440SPE)
1978/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
1979/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
1980#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
1981#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
1982#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
1983#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
1984#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
1985#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
1986
1987#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
1988 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
1989/*---------------------------------------------------------------------------+
1990| Universal interrupt controller 0 interrupts (UIC0)
1991+---------------------------------------------------------------------------*/
1992#define UIC_U0 0x80000000 /* UART 0 */
1993#define UIC_U1 0x40000000 /* UART 1 */
1994#define UIC_IIC0 0x20000000 /* IIC */
1995#define UIC_IIC1 0x10000000 /* IIC */
1996#define UIC_PIM 0x08000000 /* PCI inbound message */
1997#define UIC_PCRW 0x04000000 /* PCI command register write */
1998#define UIC_PPM 0x02000000 /* PCI power management */
1999#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
2000#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
2001#define UIC_EIR15 0x00400000 /* External intp 15 */
2002#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
2003#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
2004#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
2005#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
2006#define UIC_EIR14 0x00002000 /* External interrupt 14 */
2007#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
2008#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
2009#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
2010#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
2011#define UIC_I2OID 0x00000100 /* I2O inbound door bell */
2012#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
2013#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
2014#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
2015#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
2016#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
2017#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
2018/*---------------------------------------------------------------------------+
2019| Universal interrupt controller 1 interrupts (UIC1)
2020+---------------------------------------------------------------------------*/
2021#define UIC_EIR13 0x80000000 /* externei intp 13 */
2022#define UIC_MS 0x40000000 /* MAL SERR */
2023#define UIC_MTDE 0x20000000 /* MAL TXDE */
2024#define UIC_MRDE 0x10000000 /* MAL RXDE */
2025#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
2026#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
2027#define UIC_MTE 0x02000000 /* MAL TXEOB */
2028#define UIC_MRE 0x01000000 /* MAL RXEOB */
2029#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
2030#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
2031#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
2032#define UIC_L2C 0x00100000 /* L2 cache */
2033#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
2034#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
2035#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
2036#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
2037#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
2038#define UIC_EIR12 0x00004000 /* External interrupt 12 */
2039#define UIC_EIR11 0x00002000 /* External interrupt 11 */
2040#define UIC_EIR10 0x00001000 /* External interrupt 10 */
2041#define UIC_EIR9 0x00000800 /* External interrupt 9 */
2042#define UIC_EIR8 0x00000400 /* External interrupt 8 */
2043#define UIC_DMAE 0x00000200 /* dma error */
2044#define UIC_I2OE 0x00000100 /* i2o error */
2045#define UIC_SRE 0x00000080 /* Serial ROM error */
2046#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
2047#define UIC_EIR7 0x00000020 /* External interrupt 7 */
2048#define UIC_EIR6 0x00000010 /* External interrupt 6 */
2049#define UIC_ETH0 0x00000008 /* Ethernet 0 */
2050#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
2051#define UIC_ETH1 0x00000002 /* reserved */
2052#define UIC_XOR 0x00000001 /* xor */
2053
2054/*---------------------------------------------------------------------------+
2055| Universal interrupt controller 2 interrupts (UIC2)
2056+---------------------------------------------------------------------------*/
2057#define UIC_PEOAL 0x80000000 /* PE0 AL */
2058#define UIC_PEOVA 0x40000000 /* PE0 VPD access */
2059#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
2060#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
2061#define UIC_PE0TCR 0x08000000 /* PE0 TCR */
2062#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
2063#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
2064#define UIC_PE1AL 0x00800000 /* PE1 AL */
2065#define UIC_PE1VA 0x00400000 /* PE1 VPD access */
2066#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
2067#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
2068#define UIC_PE1TCR 0x00080000 /* PE1 TCR */
2069#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
2070#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
2071#define UIC_PE2AL 0x00008000 /* PE2 AL */
2072#define UIC_PE2VA 0x00004000 /* PE2 VPD access */
2073#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
2074#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
2075#define UIC_PE2TCR 0x00000800 /* PE2 TCR */
2076#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
2077#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
2078#define UIC_EIR5 0x00000080 /* External interrupt 5 */
2079#define UIC_EIR4 0x00000040 /* External interrupt 4 */
2080#define UIC_EIR3 0x00000020 /* External interrupt 3 */
2081#define UIC_EIR2 0x00000010 /* External interrupt 2 */
2082#define UIC_EIR1 0x00000008 /* External interrupt 1 */
2083#define UIC_EIR0 0x00000004 /* External interrupt 0 */
2084#endif /* CONFIG_440SPE */
wdenkc00b5f82002-11-03 11:12:02 +00002085
2086/*-----------------------------------------------------------------------------+
wdenk0e6d7982004-03-14 00:07:33 +00002087| External Bus Controller Bit Settings
2088+-----------------------------------------------------------------------------*/
wdenk63153492005-04-03 20:55:38 +00002089#define EBC_CFGADDR_MASK 0x0000003F
wdenk0e6d7982004-03-14 00:07:33 +00002090
wdenk63153492005-04-03 20:55:38 +00002091#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
2092#define EBC_BXCR_BS_MASK 0x000E0000
2093#define EBC_BXCR_BS_1MB 0x00000000
2094#define EBC_BXCR_BS_2MB 0x00020000
2095#define EBC_BXCR_BS_4MB 0x00040000
2096#define EBC_BXCR_BS_8MB 0x00060000
2097#define EBC_BXCR_BS_16MB 0x00080000
2098#define EBC_BXCR_BS_32MB 0x000A0000
2099#define EBC_BXCR_BS_64MB 0x000C0000
2100#define EBC_BXCR_BS_128MB 0x000E0000
2101#define EBC_BXCR_BU_MASK 0x00018000
2102#define EBC_BXCR_BU_R 0x00008000
2103#define EBC_BXCR_BU_W 0x00010000
2104#define EBC_BXCR_BU_RW 0x00018000
2105#define EBC_BXCR_BW_MASK 0x00006000
2106#define EBC_BXCR_BW_8BIT 0x00000000
2107#define EBC_BXCR_BW_16BIT 0x00002000
Stefan Roeseb79316f2005-08-15 12:31:23 +02002108#define EBC_BXCR_BW_32BIT 0x00006000
wdenk63153492005-04-03 20:55:38 +00002109#define EBC_BXAP_BME_ENABLED 0x80000000
2110#define EBC_BXAP_BME_DISABLED 0x00000000
2111#define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
2112#define EBC_BXAP_BCE_DISABLE 0x00000000
2113#define EBC_BXAP_BCE_ENABLE 0x00400000
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01002114#define EBC_BXAP_BCT_MASK 0x00300000
2115#define EBC_BXAP_BCT_2TRANS 0x00000000
2116#define EBC_BXAP_BCT_4TRANS 0x00100000
2117#define EBC_BXAP_BCT_8TRANS 0x00200000
2118#define EBC_BXAP_BCT_16TRANS 0x00300000
wdenk63153492005-04-03 20:55:38 +00002119#define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
2120#define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
2121#define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
2122#define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12)
2123#define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9)
2124#define EBC_BXAP_RE_ENABLED 0x00000100
2125#define EBC_BXAP_RE_DISABLED 0x00000000
2126#define EBC_BXAP_SOR_DELAYED 0x00000000
2127#define EBC_BXAP_SOR_NONDELAYED 0x00000080
2128#define EBC_BXAP_BEM_WRITEONLY 0x00000000
2129#define EBC_BXAP_BEM_RW 0x00000040
2130#define EBC_BXAP_PEN_DISABLED 0x00000000
wdenk0e6d7982004-03-14 00:07:33 +00002131
wdenk63153492005-04-03 20:55:38 +00002132#define EBC_CFG_LE_MASK 0x80000000
2133#define EBC_CFG_LE_UNLOCK 0x00000000
2134#define EBC_CFG_LE_LOCK 0x80000000
2135#define EBC_CFG_PTD_MASK 0x40000000
2136#define EBC_CFG_PTD_ENABLE 0x00000000
2137#define EBC_CFG_PTD_DISABLE 0x40000000
2138#define EBC_CFG_RTC_MASK 0x38000000
2139#define EBC_CFG_RTC_16PERCLK 0x00000000
2140#define EBC_CFG_RTC_32PERCLK 0x08000000
2141#define EBC_CFG_RTC_64PERCLK 0x10000000
2142#define EBC_CFG_RTC_128PERCLK 0x18000000
2143#define EBC_CFG_RTC_256PERCLK 0x20000000
2144#define EBC_CFG_RTC_512PERCLK 0x28000000
2145#define EBC_CFG_RTC_1024PERCLK 0x30000000
2146#define EBC_CFG_RTC_2048PERCLK 0x38000000
2147#define EBC_CFG_ATC_MASK 0x04000000
2148#define EBC_CFG_ATC_HI 0x00000000
2149#define EBC_CFG_ATC_PREVIOUS 0x04000000
2150#define EBC_CFG_DTC_MASK 0x02000000
2151#define EBC_CFG_DTC_HI 0x00000000
2152#define EBC_CFG_DTC_PREVIOUS 0x02000000
2153#define EBC_CFG_CTC_MASK 0x01000000
2154#define EBC_CFG_CTC_HI 0x00000000
2155#define EBC_CFG_CTC_PREVIOUS 0x01000000
2156#define EBC_CFG_OEO_MASK 0x00800000
2157#define EBC_CFG_OEO_HI 0x00000000
2158#define EBC_CFG_OEO_PREVIOUS 0x00800000
2159#define EBC_CFG_EMC_MASK 0x00400000
2160#define EBC_CFG_EMC_NONDEFAULT 0x00000000
2161#define EBC_CFG_EMC_DEFAULT 0x00400000
2162#define EBC_CFG_PME_MASK 0x00200000
2163#define EBC_CFG_PME_DISABLE 0x00000000
2164#define EBC_CFG_PME_ENABLE 0x00200000
2165#define EBC_CFG_PMT_MASK 0x001F0000
2166#define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
2167#define EBC_CFG_PR_MASK 0x0000C000
2168#define EBC_CFG_PR_16 0x00000000
2169#define EBC_CFG_PR_32 0x00004000
2170#define EBC_CFG_PR_64 0x00008000
2171#define EBC_CFG_PR_128 0x0000C000
wdenk0e6d7982004-03-14 00:07:33 +00002172
2173/*-----------------------------------------------------------------------------+
Stefan Roese6e7fb6e2005-11-29 18:18:21 +01002174| SDR0 Bit Settings
wdenk0e6d7982004-03-14 00:07:33 +00002175+-----------------------------------------------------------------------------*/
Stefan Roesedf294492007-03-08 10:06:09 +01002176#if defined(CONFIG_440SP)
2177#define SDR0_SRST 0x0200
2178
2179#define SDR0_DDR0 0x00E1
2180#define SDR0_DDR0_DPLLRST 0x80000000
2181#define SDR0_DDR0_DDRM_MASK 0x60000000
2182#define SDR0_DDR0_DDRM_DDR1 0x20000000
2183#define SDR0_DDR0_DDRM_DDR2 0x40000000
2184#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
2185#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
2186#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
2187#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
2188#endif
2189
Marian Balakowicz6c5879f2006-06-30 16:30:46 +02002190#if defined(CONFIG_440SPE)
2191#define SDR0_CP440 0x0180
2192#define SDR0_CP440_ERPN_MASK 0x30000000
2193#define SDR0_CP440_ERPN_MASK_HI 0x3000
2194#define SDR0_CP440_ERPN_MASK_LO 0x0000
2195#define SDR0_CP440_ERPN_EBC 0x10000000
2196#define SDR0_CP440_ERPN_EBC_HI 0x1000
2197#define SDR0_CP440_ERPN_EBC_LO 0x0000
2198#define SDR0_CP440_ERPN_PCI 0x20000000
2199#define SDR0_CP440_ERPN_PCI_HI 0x2000
2200#define SDR0_CP440_ERPN_PCI_LO 0x0000
2201#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2202#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2203#define SDR0_CP440_NTO1_MASK 0x00000002
2204#define SDR0_CP440_NTO1_NTOP 0x00000000
2205#define SDR0_CP440_NTO1_NTO1 0x00000002
2206#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2207#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2208#define SDR0_CFGADDR 0x00E /*already defined line 277 */
2209#define SDR0_CFGDATA 0x00F
2210
2211
2212#define SDR0_SDSTP0 0x0020
2213#define SDR0_SDSTP0_ENG_MASK 0x80000000
2214#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
2215#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
2216#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2217#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2218#define SDR0_SDSTP0_SRC_MASK 0x40000000
2219#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
2220#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
2221#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2222#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2223#define SDR0_SDSTP0_SEL_MASK 0x38000000
2224#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
2225#define SDR0_SDSTP0_SEL_CPU 0x08000000
2226#define SDR0_SDSTP0_SEL_EBC 0x28000000
2227#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
2228#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
2229#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
2230#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
2231#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
2232#define SDR0_SDSTP0_FBDV_MASK 0x0001F000
2233#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
2234#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
2235#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
2236#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
2237#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
2238#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
2239#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
2240#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
2241#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
2242#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
2243#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
2244#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
2245#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
2246#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
2247
2248
2249#define SDR0_SDSTP1 0x0021
2250#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
2251#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
2252#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
2253#define SDR0_SDSTP1_PERDV0_MASK 0x03000000
2254#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2255#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
2256#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
2257#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
2258#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
2259#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
2260#define SDR0_SDSTP1_DDR1_MODE 0x00100000
2261#define SDR0_SDSTP1_DDR2_MODE 0x00200000
2262#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
2263#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
2264#define SDR0_SDSTP1_ERPN_MASK 0x00080000
2265#define SDR0_SDSTP1_ERPN_EBC 0x00000000
2266#define SDR0_SDSTP1_ERPN_PCI 0x00080000
2267#define SDR0_SDSTP1_PAE_MASK 0x00040000
2268#define SDR0_SDSTP1_PAE_DISABLE 0x00000000
2269#define SDR0_SDSTP1_PAE_ENABLE 0x00040000
2270#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
2271#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
2272#define SDR0_SDSTP1_PHCE_MASK 0x00020000
2273#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
2274#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
2275#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
2276#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
2277#define SDR0_SDSTP1_PISE_MASK 0x00010000
2278#define SDR0_SDSTP1_PISE_DISABLE 0x00000000
2279#define SDR0_SDSTP1_PISE_ENABLE 0x00001000
2280#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
2281#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
2282#define SDR0_SDSTP1_PCWE_MASK 0x00008000
2283#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
2284#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
2285#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
2286#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
2287#define SDR0_SDSTP1_PPIM_MASK 0x00007800
2288#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
2289#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
2290#define SDR0_SDSTP1_PR64E_MASK 0x00000400
2291#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
2292#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
2293#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
2294#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
2295#define SDR0_SDSTP1_PXFS_MASK 0x00000300
2296#define SDR0_SDSTP1_PXFS_100_133 0x00000000
2297#define SDR0_SDSTP1_PXFS_66_100 0x00000100
2298#define SDR0_SDSTP1_PXFS_50_66 0x00000200
2299#define SDR0_SDSTP1_PXFS_0_50 0x00000300
2300#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
2301#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
2302#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
2303#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
2304#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
2305#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
2306#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
2307#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
2308#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
2309#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
2310#define SDR0_SDSTP1_ETH_MASK 0x00000004
2311#define SDR0_SDSTP1_ETH_10_100 0x00000000
2312#define SDR0_SDSTP1_ETH_GIGA 0x00000004
2313#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
2314#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
2315#define SDR0_SDSTP1_NTO1_MASK 0x00000001
2316#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
2317#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
2318#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
2319#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
2320
2321#define SDR0_SDSTP2 0x0022
2322#define SDR0_SDSTP2_P1AE_MASK 0x80000000
2323#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
2324#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
2325#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2326#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2327#define SDR0_SDSTP2_P1HCE_MASK 0x40000000
2328#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
2329#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
2330#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2331#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2332#define SDR0_SDSTP2_P1ISE_MASK 0x20000000
2333#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
2334#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
2335#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2336#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2337#define SDR0_SDSTP2_P1CWE_MASK 0x10000000
2338#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
2339#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
2340#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2341#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2342#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
2343#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2344#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2345#define SDR0_SDSTP2_P1R64E_MASK 0x00800000
2346#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
2347#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
2348#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2349#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2350#define SDR0_SDSTP2_P1XFS_MASK 0x00600000
2351#define SDR0_SDSTP2_P1XFS_100_133 0x00000000
2352#define SDR0_SDSTP2_P1XFS_66_100 0x00200000
2353#define SDR0_SDSTP2_P1XFS_50_66 0x00400000
2354#define SDR0_SDSTP2_P1XFS_0_50 0x00600000
2355#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2356#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2357#define SDR0_SDSTP2_P2AE_MASK 0x00040000
2358#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
2359#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
2360#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
2361#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
2362#define SDR0_SDSTP2_P2HCE_MASK 0x00020000
2363#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
2364#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
2365#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
2366#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
2367#define SDR0_SDSTP2_P2ISE_MASK 0x00010000
2368#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
2369#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
2370#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
2371#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
2372#define SDR0_SDSTP2_P2CWE_MASK 0x00008000
2373#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
2374#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
2375#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
2376#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
2377#define SDR0_SDSTP2_P2PIM_MASK 0x00007800
2378#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
2379#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
2380#define SDR0_SDSTP2_P2XFS_MASK 0x00000300
2381#define SDR0_SDSTP2_P2XFS_100_133 0x00000000
2382#define SDR0_SDSTP2_P2XFS_66_100 0x00000100
2383#define SDR0_SDSTP2_P2XFS_50_66 0x00000200
2384#define SDR0_SDSTP2_P2XFS_0_50 0x00000100
2385#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
2386#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
2387
2388#define SDR0_SDSTP3 0x0023
2389
2390#define SDR0_PINSTP 0x0040
2391#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
2392#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
2393#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
2394#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
2395#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
2396#define SDR0_SDCS 0x0060
2397#define SDR0_ECID0 0x0080
2398#define SDR0_ECID1 0x0081
2399#define SDR0_ECID2 0x0082
2400#define SDR0_JTAG 0x00C0
2401
2402#define SDR0_DDR0 0x00E1
2403#define SDR0_DDR0_DPLLRST 0x80000000
2404#define SDR0_DDR0_DDRM_MASK 0x60000000
2405