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Reinhard Meyera61a8192010-09-12 16:23:49 +02001/*
2 * (X) extracted from enc28j60.c
3 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Reinhard Meyera61a8192010-09-12 16:23:49 +02006 */
7
8#ifndef _enc28j60_h
9#define _enc28j60_h
10
11/*
12 * SPI Commands
13 *
14 * Bits 7-5: Command
15 * Bits 4-0: Register
16 */
17#define CMD_RCR(x) (0x00+((x)&0x1f)) /* Read Control Register */
18#define CMD_RBM 0x3a /* Read Buffer Memory */
19#define CMD_WCR(x) (0x40+((x)&0x1f)) /* Write Control Register */
20#define CMD_WBM 0x7a /* Write Buffer Memory */
21#define CMD_BFS(x) (0x80+((x)&0x1f)) /* Bit Field Set */
22#define CMD_BFC(x) (0xa0+((x)&0x1f)) /* Bit Field Clear */
23#define CMD_SRC 0xff /* System Reset Command */
24
25/* NEW: encode (bank number+1) in upper byte */
26
27/* Common Control Registers accessible in all Banks */
28#define CTL_REG_EIE 0x01B
29#define CTL_REG_EIR 0x01C
30#define CTL_REG_ESTAT 0x01D
31#define CTL_REG_ECON2 0x01E
32#define CTL_REG_ECON1 0x01F
33
34/* Control Registers accessible in Bank 0 */
35#define CTL_REG_ERDPTL 0x100
36#define CTL_REG_ERDPTH 0x101
37#define CTL_REG_EWRPTL 0x102
38#define CTL_REG_EWRPTH 0x103
39#define CTL_REG_ETXSTL 0x104
40#define CTL_REG_ETXSTH 0x105
41#define CTL_REG_ETXNDL 0x106
42#define CTL_REG_ETXNDH 0x107
43#define CTL_REG_ERXSTL 0x108
44#define CTL_REG_ERXSTH 0x109
45#define CTL_REG_ERXNDL 0x10A
46#define CTL_REG_ERXNDH 0x10B
47#define CTL_REG_ERXRDPTL 0x10C
48#define CTL_REG_ERXRDPTH 0x10D
49#define CTL_REG_ERXWRPTL 0x10E
50#define CTL_REG_ERXWRPTH 0x10F
51#define CTL_REG_EDMASTL 0x110
52#define CTL_REG_EDMASTH 0x111
53#define CTL_REG_EDMANDL 0x112
54#define CTL_REG_EDMANDH 0x113
55#define CTL_REG_EDMADSTL 0x114
56#define CTL_REG_EDMADSTH 0x115
57#define CTL_REG_EDMACSL 0x116
58#define CTL_REG_EDMACSH 0x117
59
60/* Control Registers accessible in Bank 1 */
61#define CTL_REG_EHT0 0x200
62#define CTL_REG_EHT1 0x201
63#define CTL_REG_EHT2 0x202
64#define CTL_REG_EHT3 0x203
65#define CTL_REG_EHT4 0x204
66#define CTL_REG_EHT5 0x205
67#define CTL_REG_EHT6 0x206
68#define CTL_REG_EHT7 0x207
69#define CTL_REG_EPMM0 0x208
70#define CTL_REG_EPMM1 0x209
71#define CTL_REG_EPMM2 0x20A
72#define CTL_REG_EPMM3 0x20B
73#define CTL_REG_EPMM4 0x20C
74#define CTL_REG_EPMM5 0x20D
75#define CTL_REG_EPMM6 0x20E
76#define CTL_REG_EPMM7 0x20F
77#define CTL_REG_EPMCSL 0x210
78#define CTL_REG_EPMCSH 0x211
79#define CTL_REG_EPMOL 0x214
80#define CTL_REG_EPMOH 0x215
81#define CTL_REG_EWOLIE 0x216
82#define CTL_REG_EWOLIR 0x217
83#define CTL_REG_ERXFCON 0x218
84#define CTL_REG_EPKTCNT 0x219
85
86/* Control Registers accessible in Bank 2 */
87#define CTL_REG_MACON1 0x300
88#define CTL_REG_MACON2 0x301
89#define CTL_REG_MACON3 0x302
90#define CTL_REG_MACON4 0x303
91#define CTL_REG_MABBIPG 0x304
92#define CTL_REG_MAIPGL 0x306
93#define CTL_REG_MAIPGH 0x307
94#define CTL_REG_MACLCON1 0x308
95#define CTL_REG_MACLCON2 0x309
96#define CTL_REG_MAMXFLL 0x30A
97#define CTL_REG_MAMXFLH 0x30B
98#define CTL_REG_MAPHSUP 0x30D
99#define CTL_REG_MICON 0x311
100#define CTL_REG_MICMD 0x312
101#define CTL_REG_MIREGADR 0x314
102#define CTL_REG_MIWRL 0x316
103#define CTL_REG_MIWRH 0x317
104#define CTL_REG_MIRDL 0x318
105#define CTL_REG_MIRDH 0x319
106
107/* Control Registers accessible in Bank 3 */
108#define CTL_REG_MAADR1 0x400
109#define CTL_REG_MAADR0 0x401
110#define CTL_REG_MAADR3 0x402
111#define CTL_REG_MAADR2 0x403
112#define CTL_REG_MAADR5 0x404
113#define CTL_REG_MAADR4 0x405
114#define CTL_REG_EBSTSD 0x406
115#define CTL_REG_EBSTCON 0x407
116#define CTL_REG_EBSTCSL 0x408
117#define CTL_REG_EBSTCSH 0x409
118#define CTL_REG_MISTAT 0x40A
119#define CTL_REG_EREVID 0x412
120#define CTL_REG_ECOCON 0x415
121#define CTL_REG_EFLOCON 0x417
122#define CTL_REG_EPAUSL 0x418
123#define CTL_REG_EPAUSH 0x419
124
125/* PHY Register */
126#define PHY_REG_PHCON1 0x00
127#define PHY_REG_PHSTAT1 0x01
128#define PHY_REG_PHID1 0x02
129#define PHY_REG_PHID2 0x03
130#define PHY_REG_PHCON2 0x10
131#define PHY_REG_PHSTAT2 0x11
132#define PHY_REG_PHLCON 0x14
133
134/* Receive Filter Register (ERXFCON) bits */
135#define ENC_RFR_UCEN 0x80
136#define ENC_RFR_ANDOR 0x40
137#define ENC_RFR_CRCEN 0x20
138#define ENC_RFR_PMEN 0x10
139#define ENC_RFR_MPEN 0x08
140#define ENC_RFR_HTEN 0x04
141#define ENC_RFR_MCEN 0x02
142#define ENC_RFR_BCEN 0x01
143
144/* ECON1 Register Bits */
145#define ENC_ECON1_TXRST 0x80
146#define ENC_ECON1_RXRST 0x40
147#define ENC_ECON1_DMAST 0x20
148#define ENC_ECON1_CSUMEN 0x10
149#define ENC_ECON1_TXRTS 0x08
150#define ENC_ECON1_RXEN 0x04
151#define ENC_ECON1_BSEL1 0x02
152#define ENC_ECON1_BSEL0 0x01
153
154/* ECON2 Register Bits */
155#define ENC_ECON2_AUTOINC 0x80
156#define ENC_ECON2_PKTDEC 0x40
157#define ENC_ECON2_PWRSV 0x20
158#define ENC_ECON2_VRPS 0x08
159
160/* EIR Register Bits */
161#define ENC_EIR_PKTIF 0x40
162#define ENC_EIR_DMAIF 0x20
163#define ENC_EIR_LINKIF 0x10
164#define ENC_EIR_TXIF 0x08
165#define ENC_EIR_WOLIF 0x04
166#define ENC_EIR_TXERIF 0x02
167#define ENC_EIR_RXERIF 0x01
168
169/* ESTAT Register Bits */
170#define ENC_ESTAT_INT 0x80
171#define ENC_ESTAT_LATECOL 0x10
172#define ENC_ESTAT_RXBUSY 0x04
173#define ENC_ESTAT_TXABRT 0x02
174#define ENC_ESTAT_CLKRDY 0x01
175
176/* EIE Register Bits */
177#define ENC_EIE_INTIE 0x80
178#define ENC_EIE_PKTIE 0x40
179#define ENC_EIE_DMAIE 0x20
180#define ENC_EIE_LINKIE 0x10
181#define ENC_EIE_TXIE 0x08
182#define ENC_EIE_WOLIE 0x04
183#define ENC_EIE_TXERIE 0x02
184#define ENC_EIE_RXERIE 0x01
185
186/* MACON1 Register Bits */
187#define ENC_MACON1_LOOPBK 0x10
188#define ENC_MACON1_TXPAUS 0x08
189#define ENC_MACON1_RXPAUS 0x04
190#define ENC_MACON1_PASSALL 0x02
191#define ENC_MACON1_MARXEN 0x01
192
193/* MACON2 Register Bits */
194#define ENC_MACON2_MARST 0x80
195#define ENC_MACON2_RNDRST 0x40
196#define ENC_MACON2_MARXRST 0x08
197#define ENC_MACON2_RFUNRST 0x04
198#define ENC_MACON2_MATXRST 0x02
199#define ENC_MACON2_TFUNRST 0x01
200
201/* MACON3 Register Bits */
202#define ENC_MACON3_PADCFG2 0x80
203#define ENC_MACON3_PADCFG1 0x40
204#define ENC_MACON3_PADCFG0 0x20
205#define ENC_MACON3_TXCRCEN 0x10
206#define ENC_MACON3_PHDRLEN 0x08
207#define ENC_MACON3_HFRMEN 0x04
208#define ENC_MACON3_FRMLNEN 0x02
209#define ENC_MACON3_FULDPX 0x01
210
211/* MACON4 Register Bits */
212#define ENC_MACON4_DEFER 0x40
213
214/* MICMD Register Bits */
215#define ENC_MICMD_MIISCAN 0x02
216#define ENC_MICMD_MIIRD 0x01
217
218/* MISTAT Register Bits */
219#define ENC_MISTAT_NVALID 0x04
220#define ENC_MISTAT_SCAN 0x02
221#define ENC_MISTAT_BUSY 0x01
222
223/* PHID1 and PHID2 values */
224#define ENC_PHID1_VALUE 0x0083
225#define ENC_PHID2_VALUE 0x1400
226#define ENC_PHID2_MASK 0xFC00
227
228/* PHCON1 values */
229#define ENC_PHCON1_PDPXMD 0x0100
230
231/* PHSTAT1 values */
232#define ENC_PHSTAT1_LLSTAT 0x0004
233
234/* PHSTAT2 values */
235#define ENC_PHSTAT2_LSTAT 0x0400
236#define ENC_PHSTAT2_DPXSTAT 0x0200
237
238#endif