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wdenkefa329c2004-03-23 20:18:25 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenkefa329c2004-03-23 20:18:25 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5200
wdenk62b4ac92004-05-05 08:31:53 +000033#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
wdenkefa329c2004-03-23 20:18:25 +000034#define CONFIG_PM520 1 /* ... on PM520 board */
35
36#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
37
wdenk49822e22004-06-19 21:19:10 +000038#define CONFIG_MISC_INIT_R
39
wdenkefa329c2004-03-23 20:18:25 +000040#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
41#define BOOTFLAG_WARM 0x02 /* Software reboot */
42
43#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
44#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
45# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
46#endif
47
48/*
49 * Serial console configuration
50 */
51#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
52#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */
53#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
54
55
56#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
57/*
58 * PCI Mapping:
59 * 0x40000000 - 0x4fffffff - PCI Memory
60 * 0x50000000 - 0x50ffffff - PCI IO Space
61 */
62#define CONFIG_PCI 1
63#define CONFIG_PCI_PNP 1
64#define CONFIG_PCI_SCAN_SHOW 1
65
66#define CONFIG_PCI_MEM_BUS 0x40000000
67#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
68#define CONFIG_PCI_MEM_SIZE 0x10000000
69
70#define CONFIG_PCI_IO_BUS 0x50000000
71#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
72#define CONFIG_PCI_IO_SIZE 0x01000000
73
74#define CONFIG_NET_MULTI 1
Marian Balakowicz63ff0042005-10-28 22:30:33 +020075#define CONFIG_MII 1
wdenkefa329c2004-03-23 20:18:25 +000076#define CONFIG_EEPRO100 1
77#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
78#undef CONFIG_NS8382X
79
80#define ADD_PCI_CMD CFG_CMD_PCI
81
82#else /* MPC5100 */
83
84#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
85
86#endif
87
wdenk49822e22004-06-19 21:19:10 +000088/* Partitions */
89#define CONFIG_DOS_PARTITION
90
91/* USB */
92#if 1
93#define CONFIG_USB_OHCI
94#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
95#define CONFIG_USB_STORAGE
96#else
97#define ADD_USB_CMD 0
98#endif
99
100#if defined(CONFIG_BOOT_ROM)
101#define ADD_DOC_CMD 0
102#else
103#define ADD_DOC_CMD CFG_CMD_DOC
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100104/* DoC requires legacy NAND for now */
105#define CFG_NAND_LEGACY
wdenk49822e22004-06-19 21:19:10 +0000106#endif
107
wdenkefa329c2004-03-23 20:18:25 +0000108/*
109 * Supported commands
110 */
wdenk414eec32005-04-02 22:37:54 +0000111#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
112 ADD_DOC_CMD | \
113 ADD_PCI_CMD | \
114 ADD_USB_CMD | \
115 CFG_CMD_BEDBUG | \
116 CFG_CMD_DATE | \
117 CFG_CMD_DHCP | \
118 CFG_CMD_EEPROM | \
119 CFG_CMD_FAT | \
120 CFG_CMD_I2C | \
121 CFG_CMD_IDE | \
122 CFG_CMD_NFS | \
123 CFG_CMD_SNTP )
wdenkefa329c2004-03-23 20:18:25 +0000124
125/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
126#include <cmd_confdefs.h>
127
128/*
129 * Autobooting
130 */
131#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenk49822e22004-06-19 21:19:10 +0000132
133#define CONFIG_PREBOOT "echo;" \
134 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
135 "echo"
136
137#undef CONFIG_BOOTARGS
138
139#define CONFIG_EXTRA_ENV_SETTINGS \
140 "netdev=eth0\0" \
141 "hostname=pm520\0" \
142 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100143 "nfsroot=${serverip}:${rootpath}\0" \
wdenk49822e22004-06-19 21:19:10 +0000144 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100145 "addip=setenv bootargs ${bootargs} " \
146 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
147 ":${hostname}:${netdev}:off panic=1\0" \
wdenk49822e22004-06-19 21:19:10 +0000148 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100149 "bootm ${kernel_addr}\0" \
wdenk49822e22004-06-19 21:19:10 +0000150 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100151 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
152 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk49822e22004-06-19 21:19:10 +0000153 "rootpath=/opt/eldk30/ppc_82xx\0" \
154 "bootfile=/tftpboot/PM520/uImage\0" \
155 ""
156
157#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkefa329c2004-03-23 20:18:25 +0000158
159#if defined(CONFIG_MPC5200)
160/*
161 * IPB Bus clocking configuration.
162 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200163#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenkefa329c2004-03-23 20:18:25 +0000164#endif
165/*
166 * I2C configuration
167 */
168#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
169#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
170
171#define CFG_I2C_SPEED 100000 /* 100 kHz */
172#define CFG_I2C_SLAVE 0x7F
173
174/*
175 * EEPROM configuration
176 */
177#define CFG_I2C_EEPROM_ADDR 0x58
178#define CFG_I2C_EEPROM_ADDR_LEN 1
179#define CFG_EEPROM_PAGE_WRITE_BITS 4
180#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
181
182/*
183 * RTC configuration
184 */
185#define CONFIG_RTC_PCF8563
186#define CFG_I2C_RTC_ADDR 0x51
187
188/*
wdenk49822e22004-06-19 21:19:10 +0000189 * Disk-On-Chip configuration
wdenkefa329c2004-03-23 20:18:25 +0000190 */
wdenk49822e22004-06-19 21:19:10 +0000191
192#define CFG_DOC_SHORT_TIMEOUT
193#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
194
195#define CFG_DOC_SUPPORT_2000
196#define CFG_DOC_SUPPORT_MILLENNIUM
197#define CFG_DOC_BASE 0xE0000000
198#define CFG_DOC_SIZE 0x00100000
199
200#if defined(CONFIG_BOOT_ROM)
201/*
202 * Flash configuration (8,16 or 32 MB)
203 * TEXT base always at 0xFFF00000
204 * ENV_ADDR always at 0xFFF40000
Wolfgang Denkc7428d42005-12-29 15:12:09 +0100205 * FLASH_BASE at 0xFA000000 for 64 MB
206 * 0xFC000000 for 32 MB
wdenk49822e22004-06-19 21:19:10 +0000207 * 0xFD000000 for 16 MB
208 * 0xFD800000 for 8 MB
209 */
Wolfgang Denkc7428d42005-12-29 15:12:09 +0100210#define CFG_FLASH_BASE 0xFA000000
211#define CFG_FLASH_SIZE 0x04000000
wdenk49822e22004-06-19 21:19:10 +0000212#define CFG_BOOTROM_BASE 0xFFF00000
213#define CFG_BOOTROM_SIZE 0x00080000
214#define CFG_ENV_ADDR (0xFDF00000 + 0x40000)
215#else
216/*
217 * Flash configuration (8,16 or 32 MB)
218 * TEXT base always at 0xFFF00000
219 * ENV_ADDR always at 0xFFF40000
Wolfgang Denkc7428d42005-12-29 15:12:09 +0100220 * FLASH_BASE at 0xFC000000 for 64 MB
221 * 0xFE000000 for 32 MB
wdenk49822e22004-06-19 21:19:10 +0000222 * 0xFF000000 for 16 MB
223 * 0xFF800000 for 8 MB
224 */
Wolfgang Denkc7428d42005-12-29 15:12:09 +0100225#define CFG_FLASH_BASE 0xFC000000
226#define CFG_FLASH_SIZE 0x04000000
wdenk49822e22004-06-19 21:19:10 +0000227#define CFG_ENV_ADDR (0xFFF00000 + 0x40000)
228#endif
wdenkefa329c2004-03-23 20:18:25 +0000229#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
230
Wolfgang Denkc7428d42005-12-29 15:12:09 +0100231#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
wdenkefa329c2004-03-23 20:18:25 +0000232
233#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
234#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
235#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
236#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
237#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
238
239#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
240
241#undef CONFIG_FLASH_16BIT /* Flash is 32-bit */
242
243
244/*
245 * Environment settings
246 */
247#define CFG_ENV_IS_IN_FLASH 1
248#define CFG_ENV_SIZE 0x10000
249#define CFG_ENV_SECT_SIZE 0x40000
250#define CONFIG_ENV_OVERWRITE 1
251
252/*
253 * Memory map
254 */
255#define CFG_MBAR 0xf0000000
256#define CFG_SDRAM_BASE 0x00000000
257#define CFG_DEFAULT_MBAR 0x80000000
258
259/* Use SRAM until RAM will be available */
260#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
261#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
262
263
264#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
265#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
266#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
267
268#define CFG_MONITOR_BASE TEXT_BASE
269#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
270# define CFG_RAMBOOT 1
271#endif
272
273#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
274#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
275#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
276
277/*
278 * Ethernet configuration
279 */
wdenk62b4ac92004-05-05 08:31:53 +0000280#define CONFIG_MPC5xxx_FEC 1
281/*
282 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
283 */
284/* #define CONFIG_FEC_10MBIT 1 */
wdenkefa329c2004-03-23 20:18:25 +0000285#define CONFIG_PHY_ADDR 0x00
286
287/*
288 * GPIO configuration
289 */
290#define CFG_GPS_PORT_CONFIG 0x10000004
291
292/*
293 * Miscellaneous configurable options
294 */
295#define CFG_LONGHELP /* undef to save memory */
296#define CFG_PROMPT "=> " /* Monitor Command Prompt */
297#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
298#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
299#else
300#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
301#endif
302#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
303#define CFG_MAXARGS 16 /* max number of command args */
304#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
305
306#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
307#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
308
309#define CFG_LOAD_ADDR 0x100000 /* default load address */
310
311#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
312
313/*
314 * Various low-level settings
315 */
316#if defined(CONFIG_MPC5200)
317#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
318#define CFG_HID0_FINAL HID0_ICE
319#else
320#define CFG_HID0_INIT 0
321#define CFG_HID0_FINAL 0
322#endif
323
wdenk49822e22004-06-19 21:19:10 +0000324#if defined(CONFIG_BOOT_ROM)
325#define CFG_BOOTCS_START CFG_BOOTROM_BASE
326#define CFG_BOOTCS_SIZE CFG_BOOTROM_SIZE
327#define CFG_BOOTCS_CFG 0x00047800
328#define CFG_CS0_START CFG_BOOTROM_BASE
329#define CFG_CS0_SIZE CFG_BOOTROM_SIZE
330#define CFG_CS1_START CFG_FLASH_BASE
331#define CFG_CS1_SIZE CFG_FLASH_SIZE
Wolfgang Denkc4b465f2006-01-13 17:00:56 +0100332#define CFG_CS1_CFG 0x0004FF00
wdenk49822e22004-06-19 21:19:10 +0000333#else
wdenkefa329c2004-03-23 20:18:25 +0000334#define CFG_BOOTCS_START CFG_FLASH_BASE
335#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
Wolfgang Denkc4b465f2006-01-13 17:00:56 +0100336#define CFG_BOOTCS_CFG 0x0004FF00
wdenkefa329c2004-03-23 20:18:25 +0000337#define CFG_CS0_START CFG_FLASH_BASE
338#define CFG_CS0_SIZE CFG_FLASH_SIZE
wdenk49822e22004-06-19 21:19:10 +0000339#define CFG_CS1_START CFG_DOC_BASE
340#define CFG_CS1_SIZE CFG_DOC_SIZE
341#define CFG_CS1_CFG 0x00047800
342#endif
wdenkefa329c2004-03-23 20:18:25 +0000343
344#define CFG_CS_BURST 0x00000000
345#define CFG_CS_DEADCYCLE 0x33333333
346
347#define CFG_RESET_ADDRESS 0xff000000
348
wdenk49822e22004-06-19 21:19:10 +0000349/*-----------------------------------------------------------------------
350 * USB stuff
351 *-----------------------------------------------------------------------
352 */
353#define CONFIG_USB_CLOCK 0x0001BBBB
354#define CONFIG_USB_CONFIG 0x00005000
355
356/*-----------------------------------------------------------------------
357 * IDE/ATA stuff Supports IDE harddisk
358 *-----------------------------------------------------------------------
359 */
360
361#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
362
363#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
364#undef CONFIG_IDE_LED /* LED for ide not supported */
365
366#undef CONFIG_IDE_RESET /* reset for ide supported */
367#define CONFIG_IDE_PREINIT
368
369#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
370#define CFG_IDE_MAXDEVICE 2 /* max. 2 drive per IDE bus */
371
372#define CFG_ATA_IDE0_OFFSET 0x0000
373
374#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
375
376/* Offset for data I/O */
377#define CFG_ATA_DATA_OFFSET (0x0060)
378
379/* Offset for normal register accesses */
380#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
381
382/* Offset for alternate registers */
383#define CFG_ATA_ALT_OFFSET (0x005C)
384
385/* Interval between registers */
386#define CFG_ATA_STRIDE 4
387
wdenkefa329c2004-03-23 20:18:25 +0000388#endif /* __CONFIG_H */