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wdenk682011f2003-06-03 23:54:09 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * Modified by Udi Finkelstein udif@udif.com
6 * For the RBC823 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * board/config.h - configuration options, board specific
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*
35 * High Level Configuration Options
36 * (easy to change)
37 */
38
39#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
40#define CONFIG_RBC823 1 /* ...on a RBC823 module */
41
42
43#if 0
44#define DEBUG 1
45#define CONFIG_LAST_STAGE_INIT
46#endif
47#define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */
48#define CONFIG_LCD 1 /* use LCD controller ... */
49#define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */
50
51#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
52#undef CONFIG_8xx_CONS_SMC1
53#undef CONFIG_8xx_CONS_NONE
54#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
55#if 1
56#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57#else
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59#endif
60
61#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
62#define CONFIG_8xx_GCLK_FREQ 48000000L
63
64#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
65
66#undef CONFIG_BOOTARGS
67#define CONFIG_BOOTCOMMAND \
68 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk682011f2003-06-03 23:54:09 +000071 "bootm"
72
73#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
74#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75
76#undef CONFIG_WATCHDOG /* watchdog disabled */
77
78#define CONFIG_STATUS_LED 1 /* Status LED enabled */
79
80#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
81
82#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
83
84#undef CONFIG_MAC_PARTITION
85#define CONFIG_DOS_PARTITION
86
87#undef CONFIG_RTC_MPC8xx /* don't use internal RTC of MPC8xx (no battery) */
88
89#define CONFIG_HARD_I2C
90#define CFG_I2C_SPEED 40000
91#define CFG_I2C_SLAVE 0xfe
wdenkb79a11c2004-03-25 15:14:43 +000092#define CFG_I2C_EEPROM_ADDR 0x50
93#define CFG_I2C_EEPROM_ADDR_LEN 1
94#define CFG_EEPROM_WRITE_BITS 4
95#define CFG_EEPROM_WRITE_DELAY_MS 10
wdenk682011f2003-06-03 23:54:09 +000096
97#define CONFIG_COMMANDS ( CFG_CMD_ALL & \
wdenk682011f2003-06-03 23:54:09 +000098 ~CFG_CMD_BSP & \
wdenkb79a11c2004-03-25 15:14:43 +000099 ~CFG_CMD_DATE & \
Wolfgang Denk2b792af2005-09-24 21:54:50 +0200100 ~CFG_CMD_DISPLAY& \
wdenk682011f2003-06-03 23:54:09 +0000101 ~CFG_CMD_DTT & \
wdenke2ffd592004-12-31 09:32:47 +0000102 ~CFG_CMD_EXT2 & \
wdenkb79a11c2004-03-25 15:14:43 +0000103 ~CFG_CMD_FDC & \
104 ~CFG_CMD_FDOS & \
105 ~CFG_CMD_HWFLOW & \
106 ~CFG_CMD_IDE & \
107 ~CFG_CMD_IRQ & \
108 ~CFG_CMD_JFFS2 & \
wdenk682011f2003-06-03 23:54:09 +0000109 ~CFG_CMD_MII & \
wdenk71f95112003-06-15 22:40:42 +0000110 ~CFG_CMD_MMC & \
wdenkb79a11c2004-03-25 15:14:43 +0000111 ~CFG_CMD_NAND & \
112 ~CFG_CMD_PCI & \
113 ~CFG_CMD_PCMCIA & \
114 ~CFG_CMD_REISER & \
115 ~CFG_CMD_SCSI & \
wdenk48abe7b2004-06-09 10:15:00 +0000116 ~CFG_CMD_SETGETDCR & \
wdenk414eec32005-04-02 22:37:54 +0000117 ~CFG_CMD_SNTP & \
wdenkb79a11c2004-03-25 15:14:43 +0000118 ~CFG_CMD_SPI & \
wdenke2ffd592004-12-31 09:32:47 +0000119 ~CFG_CMD_UNIVERSE & \
wdenkb79a11c2004-03-25 15:14:43 +0000120 ~CFG_CMD_USB & \
wdenk48abe7b2004-06-09 10:15:00 +0000121 ~CFG_CMD_VFD & \
122 ~CFG_CMD_XIMG )
wdenk682011f2003-06-03 23:54:09 +0000123
124/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
125#include <cmd_confdefs.h>
126
127/*
128 * Miscellaneous configurable options
129 */
130#define CFG_LONGHELP /* undef to save memory */
131#define CFG_PROMPT "=> " /* Monitor Command Prompt */
132#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
133#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
134#else
135#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
136#endif
137#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
138#define CFG_MAXARGS 16 /* max number of command args */
139#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
140
141#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
142#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
143
144#define CFG_LOAD_ADDR 0x0100000 /* default load address */
145
146#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
147
148#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
149
150/*
151 * Low Level Configuration Settings
152 * (address mappings, register initial values, etc.)
153 * You should know what you are doing if you make changes here.
154 */
155/*-----------------------------------------------------------------------
156 * Internal Memory Mapped Register
157 */
158#define CFG_IMMR 0xFF000000
159
160/*-----------------------------------------------------------------------
161 * Definitions for initial stack pointer and data area (in DPRAM)
162 */
163#define CFG_INIT_RAM_ADDR CFG_IMMR
164#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
165#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
166#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
167#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
172 * Please note that CFG_SDRAM_BASE _must_ start at 0
173 */
174#define CFG_SDRAM_BASE 0x00000000
175#define CFG_FLASH_BASE 0xFFF00000
176#if defined(DEBUG)
177#define CFG_MONITOR_LEN (384 << 10) /* Reserve 256 kB for Monitor */
178#else
179#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
180#endif
181#define CFG_MONITOR_BASE CFG_FLASH_BASE
182#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
183
184/*
185 * For booting Linux, the board info and command line data
186 * have to be in the first 8 MB of memory, since this is
187 * the maximum mapped by the Linux kernel during initialization.
188 */
189#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
190
191/*-----------------------------------------------------------------------
192 * FLASH organization
193 */
194#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
195#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
196
197#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
198#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
199
200#define CFG_ENV_IS_IN_FLASH 1
201#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
202#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
203
204/*-----------------------------------------------------------------------
205 * Cache Configuration
206 */
207#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
208#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
209#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
210#endif
211
212/*-----------------------------------------------------------------------
213 * SYPCR - System Protection Control 11-9
214 * SYPCR can only be written once after reset!
215 *-----------------------------------------------------------------------
216 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
217 */
218#if defined(CONFIG_WATCHDOG)
219#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
220 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
221#else
222/*
223#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
224*/
225#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWRI | SYPCR_SWP)
226#endif
227
228/*-----------------------------------------------------------------------
229 * SIUMCR - SIU Module Configuration 11-6
230 *-----------------------------------------------------------------------
231 * PCMCIA config., multi-function pin tri-state
232 */
233#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_FRC)
234
235/*-----------------------------------------------------------------------
236 * TBSCR - Time Base Status and Control 11-26
237 *-----------------------------------------------------------------------
238 * Clear Reference Interrupt Status, Timebase freezing enabled
239 */
240#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
241
242/*-----------------------------------------------------------------------
243 * RTCSC - Real-Time Clock Status and Control Register 11-27
244 *-----------------------------------------------------------------------
245 */
246#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
247
248/*-----------------------------------------------------------------------
249 * PISCR - Periodic Interrupt Status and Control 11-31
250 *-----------------------------------------------------------------------
251 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
252 */
253#define CFG_PISCR (PISCR_PS | PISCR_PITF)
254
255/*-----------------------------------------------------------------------
256 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
257 *-----------------------------------------------------------------------
258 * Reset PLL lock status sticky bit, timer expired status bit and timer
259 * interrupt status bit
260 *
261 */
262
263/*
264 * for 48 MHz, we use a 4 MHz clock * 12
265 */
266#define CFG_PLPRCR \
267 ( (12-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_LOLRE )
268
269/*-----------------------------------------------------------------------
270 * SCCR - System Clock and reset Control Register 15-27
271 *-----------------------------------------------------------------------
272 * Set clock output, timebase and RTC source and divider,
273 * power management and some other internal clocks
274 */
275#define SCCR_MASK SCCR_EBDF11
276#define CFG_SCCR (SCCR_RTDIV | SCCR_RTSEL | SCCR_CRQEN | \
277 SCCR_PRQEN | SCCR_EBDF00 | \
278 SCCR_COM01 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
279 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD001 | \
280 SCCR_DFALCD00)
281
282#ifdef NOT_USED
283/*-----------------------------------------------------------------------
284 * PCMCIA stuff
285 *-----------------------------------------------------------------------
286 *
287 */
288#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
289#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
290#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
291#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
292#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
293#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
294#define CFG_PCMCIA_IO_ADDR (0xEC000000)
295#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
296
297/*-----------------------------------------------------------------------
298 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
299 *-----------------------------------------------------------------------
300 */
301
302#define CONFIG_IDE_PCCARD 1 /* Use IDE with PC Card Adapter */
303
304#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
305#undef CONFIG_IDE_LED /* LED for ide not supported */
306#undef CONFIG_IDE_RESET /* reset for ide not supported */
307
308#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
309#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
310
311#define CFG_ATA_IDE0_OFFSET 0x0000
312
313#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
314
315/* Offset for data I/O */
316#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
317
318/* Offset for normal register accesses */
319#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
320
321/* Offset for alternate registers */
322#define CFG_ATA_ALT_OFFSET 0x0100
323
324#endif
325
326/************************************************************
327 * Disk-On-Chip configuration
328 ************************************************************/
329#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
330#define CFG_DOC_SHORT_TIMEOUT
331#define CFG_DOC_SUPPORT_2000
332#define CFG_DOC_SUPPORT_MILLENNIUM
333
334/*-----------------------------------------------------------------------
335 *
336 *-----------------------------------------------------------------------
337 *
338 */
339/*#define CFG_DER 0x2002000F*/
340#define CFG_DER 0
341
342/*
343 * Init Memory Controller:
344 *
345 * BR0/1 and OR0/1 (FLASH)
346 */
347
348#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
349#define FLASH_BASE1_PRELIM 0x04000000 /* D.O.C Millenium */
350
351/* used to re-map FLASH both when starting from SRAM or FLASH:
352 * restrict access enough to keep SRAM working (if any)
353 * but not too much to meddle with FLASH accesses
354 */
355#define CFG_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
356
357/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 7, EHTR = 1 */
358#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_BI | OR_SCY_7_CLK | OR_EHTR)
359
360#define CFG_OR_TIMING_MSYS (OR_ACS_DIV1 | OR_BI)
361
362#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
363#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V)
364
365#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_MSYS)
366#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | \
367 BR_PS_8 | BR_V)
368
369/*
370 * BR4 and OR4 (SDRAM)
371 *
372 */
373#define SDRAM_BASE4_PRELIM 0x00000000 /* SDRAM bank #0 */
374#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
375
376/*
377 * SDRAM timing:
378 */
379#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM)
380
381#define CFG_OR4_PRELIM (~(SDRAM_MAX_SIZE-1) | CFG_OR_TIMING_SDRAM )
382#define CFG_BR4_PRELIM ((SDRAM_BASE4_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
383
384/*
385 * Memory Periodic Timer Prescaler
386 */
387
388/* periodic timer for refresh */
389#define CFG_MAMR_PTA 187 /* start with divider for 48 MHz */
390
391/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
392#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
393#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
394
395/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
396#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
397#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
398
399/*
400 * MAMR settings for SDRAM
401 */
402
403/* 8 column SDRAM */
404#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
405 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
406 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
407/* 9 column SDRAM */
408#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
409 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
410 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
411
412
413/*
414 * Internal Definitions
415 *
416 * Boot Flags
417 */
418#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
419#define BOOTFLAG_WARM 0x02 /* Software reboot */
420
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200421/*
422 * JFFS2 partitions
423 *
424 */
425/* No command line, one static partition, whole device */
426#undef CONFIG_JFFS2_CMDLINE
427#define CONFIG_JFFS2_DEV "nor0"
428#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
429#define CONFIG_JFFS2_PART_OFFSET 0x00000000
430
431/* mtdparts command line support */
432/* Note: fake mtd_id used, no linux mtd map file */
433/*
434#define CONFIG_JFFS2_CMDLINE
435#define MTDIDS_DEFAULT ""
436#define MTDPARTS_DEFAULT ""
437*/
438
wdenk682011f2003-06-03 23:54:09 +0000439#endif /* __CONFIG_H */