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Michael Walle7f900ea2021-10-13 18:14:26 +02001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Yuantian Tangd4ad1112019-04-10 16:43:33 +08002/*
Michael Walle7f900ea2021-10-13 18:14:26 +02003 * Device Tree Include file for NXP Layerscape-1028A family SoC.
Yuantian Tangd4ad1112019-04-10 16:43:33 +08004 *
Michael Walle7f900ea2021-10-13 18:14:26 +02005 * Copyright 2018-2020 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
Yuantian Tangd4ad1112019-04-10 16:43:33 +08008 *
9 */
10
Michael Walle7f900ea2021-10-13 18:14:26 +020011#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
Michael Walle3ffe0902019-12-18 00:10:00 +010012#include <dt-bindings/interrupt-controller/arm-gic.h>
Michael Walle7f900ea2021-10-13 18:14:26 +020013#include <dt-bindings/thermal/thermal.h>
Michael Walle3ffe0902019-12-18 00:10:00 +010014
Yuantian Tangd4ad1112019-04-10 16:43:33 +080015/ {
16 compatible = "fsl,ls1028a";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
Michael Walle7f900ea2021-10-13 18:14:26 +020021 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu0: cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a72";
28 reg = <0x0>;
29 enable-method = "psci";
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 next-level-cache = <&l2>;
32 cpu-idle-states = <&CPU_PW20>;
33 #cooling-cells = <2>;
34 };
35
36 cpu1: cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a72";
39 reg = <0x1>;
40 enable-method = "psci";
41 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 next-level-cache = <&l2>;
43 cpu-idle-states = <&CPU_PW20>;
44 #cooling-cells = <2>;
45 };
46
47 l2: l2-cache {
48 compatible = "cache";
49 };
50 };
51
52 idle-states {
53 /*
Michal Simek1be82af2023-05-17 09:17:16 +020054 * PSCI node is not added default, U-Boot will add missing
Michael Walle7f900ea2021-10-13 18:14:26 +020055 * parts if it determines to use PSCI.
56 */
57 entry-method = "psci";
58
59 CPU_PW20: cpu-pw20 {
60 compatible = "arm,idle-state";
61 idle-state-name = "PW20";
62 arm,psci-suspend-param = <0x0>;
63 entry-latency-us = <2000>;
64 exit-latency-us = <2000>;
65 min-residency-us = <6000>;
66 };
67 };
68
Yuantian Tangd4ad1112019-04-10 16:43:33 +080069 sysclk: sysclk {
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <100000000>;
73 clock-output-names = "sysclk";
74 };
75
Michael Walle7f900ea2021-10-13 18:14:26 +020076 osc_27m: clock-osc-27m {
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <27000000>;
80 clock-output-names = "phy_27m";
81 };
82
83 dpclk: clock-controller@f1f0000 {
84 compatible = "fsl,ls1028a-plldig";
85 reg = <0x0 0xf1f0000 0x0 0xffff>;
86 #clock-cells = <0>;
87 clocks = <&osc_27m>;
88 };
89
90 firmware {
91 optee: optee {
92 compatible = "linaro,optee-tz";
93 method = "smc";
94 status = "disabled";
95 };
96 };
97
98 reboot {
99 compatible ="syscon-reboot";
100 regmap = <&rst>;
101 offset = <0>;
102 mask = <0x02>;
Yuantian Tangd4ad1112019-04-10 16:43:33 +0800103 };
104
105 timer {
106 compatible = "arm,armv8-timer";
Michael Walle3ffe0902019-12-18 00:10:00 +0100107 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
108 IRQ_TYPE_LEVEL_LOW)>,
109 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
110 IRQ_TYPE_LEVEL_LOW)>,
111 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
112 IRQ_TYPE_LEVEL_LOW)>,
113 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
114 IRQ_TYPE_LEVEL_LOW)>;
Yuantian Tangd4ad1112019-04-10 16:43:33 +0800115 };
116
Michael Walle7f900ea2021-10-13 18:14:26 +0200117 pmu {
118 compatible = "arm,cortex-a72-pmu";
119 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
120 };
121
122 gic: interrupt-controller@6000000 {
123 compatible= "arm,gic-v3";
124 #address-cells = <2>;
125 #size-cells = <2>;
126 ranges;
127 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
128 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
129 #interrupt-cells= <3>;
130 interrupt-controller;
131 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
132 IRQ_TYPE_LEVEL_LOW)>;
133 its: gic-its@6020000 {
134 compatible = "arm,gic-v3-its";
135 msi-controller;
136 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
137 };
138 };
139
140 thermal-zones {
141 ddr-controller {
142 polling-delay-passive = <1000>;
143 polling-delay = <5000>;
144 thermal-sensors = <&tmu 0>;
145
146 trips {
147 ddr-ctrler-alert {
148 temperature = <85000>;
149 hysteresis = <2000>;
150 type = "passive";
151 };
152
153 ddr-ctrler-crit {
154 temperature = <95000>;
155 hysteresis = <2000>;
156 type = "critical";
157 };
158 };
159 };
160
161 core-cluster {
162 polling-delay-passive = <1000>;
163 polling-delay = <5000>;
164 thermal-sensors = <&tmu 1>;
165
166 trips {
167 core_cluster_alert: core-cluster-alert {
168 temperature = <85000>;
169 hysteresis = <2000>;
170 type = "passive";
171 };
172
173 core_cluster_crit: core-cluster-crit {
174 temperature = <95000>;
175 hysteresis = <2000>;
176 type = "critical";
177 };
178 };
179
180 cooling-maps {
181 map0 {
182 trip = <&core_cluster_alert>;
183 cooling-device =
184 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
186 };
187 };
188 };
189 };
190
Michael Wallecd80d5d2021-10-13 18:14:03 +0200191 soc: soc {
192 compatible = "simple-bus";
193 #address-cells = <2>;
194 #size-cells = <2>;
195 ranges;
Michael Walle9b38ba52021-10-13 18:14:04 +0200196
Michael Walle7f900ea2021-10-13 18:14:26 +0200197 ddr: memory-controller@1080000 {
198 compatible = "fsl,qoriq-memory-controller";
199 reg = <0x0 0x1080000 0x0 0x1000>;
200 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
201 little-endian;
202 };
203
204 dcfg: syscon@1e00000 {
205 #address-cells = <1>;
206 #size-cells = <1>;
207 compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
208 reg = <0x0 0x1e00000 0x0 0x10000>;
209 ranges = <0x0 0x0 0x1e00000 0x10000>;
210 little-endian;
211
212 fspi_clk: clock-controller@900 {
213 compatible = "fsl,ls1028a-flexspi-clk";
214 reg = <0x900 0x4>;
215 #clock-cells = <0>;
216 clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
217 clock-output-names = "fspi_clk";
218 };
219 };
220
221 rst: syscon@1e60000 {
222 compatible = "syscon";
223 reg = <0x0 0x1e60000 0x0 0x10000>;
224 little-endian;
225 };
226
227 scfg: syscon@1fc0000 {
228 compatible = "fsl,ls1028a-scfg", "syscon";
229 reg = <0x0 0x1fc0000 0x0 0x10000>;
230 big-endian;
231 };
232
233 clockgen: clock-controller@1300000 {
Michael Walle9b38ba52021-10-13 18:14:04 +0200234 compatible = "fsl,ls1028a-clockgen";
235 reg = <0x0 0x1300000 0x0 0xa0000>;
236 #clock-cells = <2>;
237 clocks = <&sysclk>;
238 };
Michael Wallefb19c6b2021-10-13 18:14:05 +0200239
240 i2c0: i2c@2000000 {
241 compatible = "fsl,vf610-i2c";
242 #address-cells = <1>;
243 #size-cells = <0>;
244 reg = <0x0 0x2000000 0x0 0x10000>;
245 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200246 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
247 QORIQ_CLK_PLL_DIV(4)>;
Michael Wallefb19c6b2021-10-13 18:14:05 +0200248 status = "disabled";
249 };
250
251 i2c1: i2c@2010000 {
252 compatible = "fsl,vf610-i2c";
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg = <0x0 0x2010000 0x0 0x10000>;
256 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200257 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
258 QORIQ_CLK_PLL_DIV(4)>;
Michael Wallefb19c6b2021-10-13 18:14:05 +0200259 status = "disabled";
260 };
261
262 i2c2: i2c@2020000 {
263 compatible = "fsl,vf610-i2c";
264 #address-cells = <1>;
265 #size-cells = <0>;
266 reg = <0x0 0x2020000 0x0 0x10000>;
267 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200268 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
269 QORIQ_CLK_PLL_DIV(4)>;
Michael Wallefb19c6b2021-10-13 18:14:05 +0200270 status = "disabled";
271 };
272
273 i2c3: i2c@2030000 {
274 compatible = "fsl,vf610-i2c";
275 #address-cells = <1>;
276 #size-cells = <0>;
277 reg = <0x0 0x2030000 0x0 0x10000>;
278 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200279 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
280 QORIQ_CLK_PLL_DIV(4)>;
Michael Wallefb19c6b2021-10-13 18:14:05 +0200281 status = "disabled";
282 };
283
284 i2c4: i2c@2040000 {
285 compatible = "fsl,vf610-i2c";
286 #address-cells = <1>;
287 #size-cells = <0>;
288 reg = <0x0 0x2040000 0x0 0x10000>;
289 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200290 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
291 QORIQ_CLK_PLL_DIV(4)>;
Michael Wallefb19c6b2021-10-13 18:14:05 +0200292 status = "disabled";
293 };
294
295 i2c5: i2c@2050000 {
296 compatible = "fsl,vf610-i2c";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 reg = <0x0 0x2050000 0x0 0x10000>;
300 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200301 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
302 QORIQ_CLK_PLL_DIV(4)>;
Michael Wallefb19c6b2021-10-13 18:14:05 +0200303 status = "disabled";
304 };
305
306 i2c6: i2c@2060000 {
307 compatible = "fsl,vf610-i2c";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 reg = <0x0 0x2060000 0x0 0x10000>;
311 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200312 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
313 QORIQ_CLK_PLL_DIV(4)>;
Michael Wallefb19c6b2021-10-13 18:14:05 +0200314 status = "disabled";
315 };
316
317 i2c7: i2c@2070000 {
318 compatible = "fsl,vf610-i2c";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 reg = <0x0 0x2070000 0x0 0x10000>;
322 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200323 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
324 QORIQ_CLK_PLL_DIV(4)>;
Michael Wallefb19c6b2021-10-13 18:14:05 +0200325 status = "disabled";
326 };
Michael Wallef02f2f92021-10-13 18:14:06 +0200327
Michael Walle7f900ea2021-10-13 18:14:26 +0200328 fspi: spi@20c0000 {
Michael Wallef02f2f92021-10-13 18:14:06 +0200329 compatible = "nxp,lx2160a-fspi";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 reg = <0x0 0x20c0000 0x0 0x10000>,
333 <0x0 0x20000000 0x0 0x10000000>;
334 reg-names = "fspi_base", "fspi_mmap";
Michael Wallef02f2f92021-10-13 18:14:06 +0200335 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200336 clocks = <&fspi_clk>, <&fspi_clk>;
337 clock-names = "fspi_en", "fspi";
Michael Wallef02f2f92021-10-13 18:14:06 +0200338 status = "disabled";
339 };
Michael Wallefbddc272021-10-13 18:14:07 +0200340
Michael Walle7f900ea2021-10-13 18:14:26 +0200341 dspi0: spi@2100000 {
Michael Walle765afe72021-10-13 18:14:17 +0200342 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
Michael Wallefbddc272021-10-13 18:14:07 +0200343 #address-cells = <1>;
344 #size-cells = <0>;
345 reg = <0x0 0x2100000 0x0 0x10000>;
346 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
347 clock-names = "dspi";
Michael Walle7f900ea2021-10-13 18:14:26 +0200348 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
349 QORIQ_CLK_PLL_DIV(2)>;
350 dmas = <&edma0 0 62>, <&edma0 0 60>;
351 dma-names = "tx", "rx";
352 spi-num-chipselects = <4>;
353 little-endian;
Michael Wallefbddc272021-10-13 18:14:07 +0200354 status = "disabled";
355 };
356
Michael Walle7f900ea2021-10-13 18:14:26 +0200357 dspi1: spi@2110000 {
Michael Walle765afe72021-10-13 18:14:17 +0200358 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
Michael Wallefbddc272021-10-13 18:14:07 +0200359 #address-cells = <1>;
360 #size-cells = <0>;
361 reg = <0x0 0x2110000 0x0 0x10000>;
362 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
363 clock-names = "dspi";
Michael Walle7f900ea2021-10-13 18:14:26 +0200364 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
365 QORIQ_CLK_PLL_DIV(2)>;
366 dmas = <&edma0 0 58>, <&edma0 0 56>;
367 dma-names = "tx", "rx";
368 spi-num-chipselects = <4>;
Michael Wallefbddc272021-10-13 18:14:07 +0200369 little-endian;
370 status = "disabled";
371 };
372
Michael Walle7f900ea2021-10-13 18:14:26 +0200373 dspi2: spi@2120000 {
Michael Walle765afe72021-10-13 18:14:17 +0200374 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
Michael Wallefbddc272021-10-13 18:14:07 +0200375 #address-cells = <1>;
376 #size-cells = <0>;
377 reg = <0x0 0x2120000 0x0 0x10000>;
378 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
379 clock-names = "dspi";
Michael Walle7f900ea2021-10-13 18:14:26 +0200380 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
381 QORIQ_CLK_PLL_DIV(2)>;
382 dmas = <&edma0 0 54>, <&edma0 0 2>;
383 dma-names = "tx", "rx";
384 spi-num-chipselects = <3>;
Michael Wallefbddc272021-10-13 18:14:07 +0200385 little-endian;
386 status = "disabled";
387 };
388
Michael Walle7f900ea2021-10-13 18:14:26 +0200389 esdhc: mmc@2140000 {
390 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
Michael Wallefbddc272021-10-13 18:14:07 +0200391 reg = <0x0 0x2140000 0x0 0x10000>;
392 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200393 clock-frequency = <0>; /* fixed up by bootloader */
394 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
395 voltage-ranges = <1800 1800 3300 3300>;
396 sdhci,auto-cmd12;
397 little-endian;
Michael Wallefbddc272021-10-13 18:14:07 +0200398 bus-width = <4>;
399 status = "disabled";
400 };
401
Michael Walle7f900ea2021-10-13 18:14:26 +0200402 esdhc1: mmc@2150000 {
403 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
Michael Wallefbddc272021-10-13 18:14:07 +0200404 reg = <0x0 0x2150000 0x0 0x10000>;
405 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200406 clock-frequency = <0>; /* fixed up by bootloader */
407 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
408 voltage-ranges = <1800 1800>;
409 sdhci,auto-cmd12;
Michael Wallefbddc272021-10-13 18:14:07 +0200410 non-removable;
Michael Walle7f900ea2021-10-13 18:14:26 +0200411 little-endian;
Michael Wallefbddc272021-10-13 18:14:07 +0200412 bus-width = <4>;
413 status = "disabled";
414 };
Michael Walle44800f22021-10-13 18:14:08 +0200415
Michael Walle7f900ea2021-10-13 18:14:26 +0200416 can0: can@2180000 {
417 compatible = "fsl,lx2160ar1-flexcan";
418 reg = <0x0 0x2180000 0x0 0x10000>;
419 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
421 QORIQ_CLK_PLL_DIV(2)>,
422 <&clockgen QORIQ_CLK_PLATFORM_PLL
423 QORIQ_CLK_PLL_DIV(2)>;
424 clock-names = "ipg", "per";
425 status = "disabled";
426 };
427
428 can1: can@2190000 {
429 compatible = "fsl,lx2160ar1-flexcan";
430 reg = <0x0 0x2190000 0x0 0x10000>;
431 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
433 QORIQ_CLK_PLL_DIV(2)>,
434 <&clockgen QORIQ_CLK_PLATFORM_PLL
435 QORIQ_CLK_PLL_DIV(2)>;
436 clock-names = "ipg", "per";
437 status = "disabled";
438 };
439
Michael Wallec816dd02021-10-13 18:14:15 +0200440 duart0: serial@21c0500 {
Michael Walle44800f22021-10-13 18:14:08 +0200441 compatible = "fsl,ns16550", "ns16550a";
Michael Walle7f900ea2021-10-13 18:14:26 +0200442 reg = <0x00 0x21c0500 0x0 0x100>;
Michael Walle44800f22021-10-13 18:14:08 +0200443 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200444 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
445 QORIQ_CLK_PLL_DIV(2)>;
Michael Walle44800f22021-10-13 18:14:08 +0200446 status = "disabled";
447 };
448
Michael Wallec816dd02021-10-13 18:14:15 +0200449 duart1: serial@21c0600 {
Michael Walle44800f22021-10-13 18:14:08 +0200450 compatible = "fsl,ns16550", "ns16550a";
Michael Walle7f900ea2021-10-13 18:14:26 +0200451 reg = <0x00 0x21c0600 0x0 0x100>;
Michael Walle44800f22021-10-13 18:14:08 +0200452 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200453 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
454 QORIQ_CLK_PLL_DIV(2)>;
Michael Walle44800f22021-10-13 18:14:08 +0200455 status = "disabled";
456 };
Michael Walleebcd6d72021-10-13 18:14:09 +0200457
Michael Walle7f900ea2021-10-13 18:14:26 +0200458
Michael Walleebcd6d72021-10-13 18:14:09 +0200459 lpuart0: serial@2260000 {
Michael Wallec9bf9af2021-10-13 18:14:19 +0200460 compatible = "fsl,ls1028a-lpuart";
Michael Walleebcd6d72021-10-13 18:14:09 +0200461 reg = <0x0 0x2260000 0x0 0x1000>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200462 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
464 QORIQ_CLK_PLL_DIV(2)>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200465 clock-names = "ipg";
Michael Walle7f900ea2021-10-13 18:14:26 +0200466 dma-names = "rx","tx";
467 dmas = <&edma0 1 32>,
468 <&edma0 1 33>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200469 status = "disabled";
470 };
471
472 lpuart1: serial@2270000 {
Michael Wallec9bf9af2021-10-13 18:14:19 +0200473 compatible = "fsl,ls1028a-lpuart";
Michael Walleebcd6d72021-10-13 18:14:09 +0200474 reg = <0x0 0x2270000 0x0 0x1000>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200475 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
477 QORIQ_CLK_PLL_DIV(2)>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200478 clock-names = "ipg";
Michael Walle7f900ea2021-10-13 18:14:26 +0200479 dma-names = "rx","tx";
480 dmas = <&edma0 1 30>,
481 <&edma0 1 31>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200482 status = "disabled";
483 };
484
485 lpuart2: serial@2280000 {
Michael Wallec9bf9af2021-10-13 18:14:19 +0200486 compatible = "fsl,ls1028a-lpuart";
Michael Walleebcd6d72021-10-13 18:14:09 +0200487 reg = <0x0 0x2280000 0x0 0x1000>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200488 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
490 QORIQ_CLK_PLL_DIV(2)>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200491 clock-names = "ipg";
Michael Walle7f900ea2021-10-13 18:14:26 +0200492 dma-names = "rx","tx";
493 dmas = <&edma0 1 28>,
494 <&edma0 1 29>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200495 status = "disabled";
496 };
497
498 lpuart3: serial@2290000 {
Michael Wallec9bf9af2021-10-13 18:14:19 +0200499 compatible = "fsl,ls1028a-lpuart";
Michael Walleebcd6d72021-10-13 18:14:09 +0200500 reg = <0x0 0x2290000 0x0 0x1000>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200501 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
503 QORIQ_CLK_PLL_DIV(2)>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200504 clock-names = "ipg";
Michael Walle7f900ea2021-10-13 18:14:26 +0200505 dma-names = "rx","tx";
506 dmas = <&edma0 1 26>,
507 <&edma0 1 27>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200508 status = "disabled";
509 };
510
511 lpuart4: serial@22a0000 {
Michael Wallec9bf9af2021-10-13 18:14:19 +0200512 compatible = "fsl,ls1028a-lpuart";
Michael Walleebcd6d72021-10-13 18:14:09 +0200513 reg = <0x0 0x22a0000 0x0 0x1000>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200514 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
516 QORIQ_CLK_PLL_DIV(2)>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200517 clock-names = "ipg";
Michael Walle7f900ea2021-10-13 18:14:26 +0200518 dma-names = "rx","tx";
519 dmas = <&edma0 1 24>,
520 <&edma0 1 25>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200521 status = "disabled";
522 };
523
524 lpuart5: serial@22b0000 {
Michael Wallec9bf9af2021-10-13 18:14:19 +0200525 compatible = "fsl,ls1028a-lpuart";
Michael Walleebcd6d72021-10-13 18:14:09 +0200526 reg = <0x0 0x22b0000 0x0 0x1000>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200527 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
529 QORIQ_CLK_PLL_DIV(2)>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200530 clock-names = "ipg";
Michael Walle7f900ea2021-10-13 18:14:26 +0200531 dma-names = "rx","tx";
532 dmas = <&edma0 1 22>,
533 <&edma0 1 23>;
Michael Walleebcd6d72021-10-13 18:14:09 +0200534 status = "disabled";
535 };
Michael Walle65da65f2021-10-13 18:14:10 +0200536
Michael Walle7f900ea2021-10-13 18:14:26 +0200537 edma0: dma-controller@22c0000 {
538 #dma-cells = <2>;
539 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
540 reg = <0x0 0x22c0000 0x0 0x10000>,
541 <0x0 0x22d0000 0x0 0x10000>,
542 <0x0 0x22e0000 0x0 0x10000>;
543 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
545 interrupt-names = "edma-tx", "edma-err";
546 dma-channels = <32>;
547 clock-names = "dmamux0", "dmamux1";
548 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
549 QORIQ_CLK_PLL_DIV(2)>,
550 <&clockgen QORIQ_CLK_PLATFORM_PLL
551 QORIQ_CLK_PLL_DIV(2)>;
552 };
553
Michael Wallec816dd02021-10-13 18:14:15 +0200554 gpio1: gpio@2300000 {
Michael Walle65da65f2021-10-13 18:14:10 +0200555 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
556 reg = <0x0 0x2300000 0x0 0x10000>;
557 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
558 gpio-controller;
559 #gpio-cells = <2>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
562 little-endian;
563 };
564
Michael Wallec816dd02021-10-13 18:14:15 +0200565 gpio2: gpio@2310000 {
Michael Walle65da65f2021-10-13 18:14:10 +0200566 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
567 reg = <0x0 0x2310000 0x0 0x10000>;
568 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
569 gpio-controller;
570 #gpio-cells = <2>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 little-endian;
574 };
575
Michael Wallec816dd02021-10-13 18:14:15 +0200576 gpio3: gpio@2320000 {
Michael Walle65da65f2021-10-13 18:14:10 +0200577 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
578 reg = <0x0 0x2320000 0x0 0x10000>;
579 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
580 gpio-controller;
581 #gpio-cells = <2>;
582 interrupt-controller;
583 #interrupt-cells = <2>;
584 little-endian;
585 };
Michael Walle659fafc2021-10-13 18:14:11 +0200586
Michael Walle7f900ea2021-10-13 18:14:26 +0200587 usb0: usb@3100000 {
Michael Walle8f176eb2021-10-13 18:14:21 +0200588 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
Michael Walle659fafc2021-10-13 18:14:11 +0200589 reg = <0x0 0x3100000 0x0 0x10000>;
590 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
591 dr_mode = "host";
Michael Walle7f900ea2021-10-13 18:14:26 +0200592 snps,dis_rxdet_inp3_quirk;
593 snps,quirk-frame-length-adjustment = <0x20>;
594 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
Michael Walle659fafc2021-10-13 18:14:11 +0200595 };
596
Michael Walle7f900ea2021-10-13 18:14:26 +0200597 usb1: usb@3110000 {
Michael Walle8f176eb2021-10-13 18:14:21 +0200598 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
Michael Walle659fafc2021-10-13 18:14:11 +0200599 reg = <0x0 0x3110000 0x0 0x10000>;
600 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
601 dr_mode = "host";
Michael Walle7f900ea2021-10-13 18:14:26 +0200602 snps,dis_rxdet_inp3_quirk;
603 snps,quirk-frame-length-adjustment = <0x20>;
604 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
Michael Walle659fafc2021-10-13 18:14:11 +0200605 };
606
607 sata: sata@3200000 {
608 compatible = "fsl,ls1028a-ahci";
Michael Walle7f900ea2021-10-13 18:14:26 +0200609 reg = <0x0 0x3200000 0x0 0x10000>,
610 <0x7 0x100520 0x0 0x4>;
Michael Wallecde9b142021-10-13 18:14:20 +0200611 reg-names = "ahci", "sata-ecc";
Michael Walle659fafc2021-10-13 18:14:11 +0200612 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200613 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
614 QORIQ_CLK_PLL_DIV(2)>;
Michael Walle659fafc2021-10-13 18:14:11 +0200615 status = "disabled";
616 };
Michael Walle3c5c4772021-10-13 18:14:12 +0200617
618 pcie1: pcie@3400000 {
Michael Wallee10da1f2021-10-13 18:14:22 +0200619 compatible = "fsl,ls1028a-pcie";
620 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
621 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
622 reg-names = "regs", "config";
Michael Walle7f900ea2021-10-13 18:14:26 +0200623 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
624 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
625 interrupt-names = "pme", "aer";
Michael Walle3c5c4772021-10-13 18:14:12 +0200626 #address-cells = <3>;
627 #size-cells = <2>;
628 device_type = "pci";
Michael Walle7f900ea2021-10-13 18:14:26 +0200629 dma-coherent;
630 num-viewport = <8>;
Michael Walle3c5c4772021-10-13 18:14:12 +0200631 bus-range = <0x0 0xff>;
Michael Walle938d9352021-10-13 18:14:24 +0200632 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
Michael Walle3c5c4772021-10-13 18:14:12 +0200633 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
Michael Walle7f900ea2021-10-13 18:14:26 +0200634 msi-parent = <&its>;
635 #interrupt-cells = <1>;
636 interrupt-map-mask = <0 0 0 7>;
637 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
638 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
639 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
640 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
641 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
Michael Walled08011d2021-10-13 18:14:25 +0200642 status = "disabled";
Michael Walle3c5c4772021-10-13 18:14:12 +0200643 };
644
645 pcie2: pcie@3500000 {
Michael Wallee10da1f2021-10-13 18:14:22 +0200646 compatible = "fsl,ls1028a-pcie";
647 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
648 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
649 reg-names = "regs", "config";
Michael Walle7f900ea2021-10-13 18:14:26 +0200650 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
652 interrupt-names = "pme", "aer";
Michael Walle3c5c4772021-10-13 18:14:12 +0200653 #address-cells = <3>;
654 #size-cells = <2>;
655 device_type = "pci";
Michael Walle7f900ea2021-10-13 18:14:26 +0200656 dma-coherent;
657 num-viewport = <8>;
Michael Walle3c5c4772021-10-13 18:14:12 +0200658 bus-range = <0x0 0xff>;
Michael Walle938d9352021-10-13 18:14:24 +0200659 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
Michael Walle3c5c4772021-10-13 18:14:12 +0200660 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
Michael Walle7f900ea2021-10-13 18:14:26 +0200661 msi-parent = <&its>;
662 #interrupt-cells = <1>;
663 interrupt-map-mask = <0 0 0 7>;
664 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
665 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
666 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
667 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
668 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
Michael Walled08011d2021-10-13 18:14:25 +0200669 status = "disabled";
Michael Walle3c5c4772021-10-13 18:14:12 +0200670 };
Michael Walle575205c2021-10-13 18:14:13 +0200671
Michael Walle7f900ea2021-10-13 18:14:26 +0200672 smmu: iommu@5000000 {
673 compatible = "arm,mmu-500";
674 reg = <0 0x5000000 0 0x800000>;
675 #global-interrupts = <8>;
676 #iommu-cells = <1>;
677 stream-match-mask = <0x7c00>;
678 /* global secure fault */
679 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
680 /* combined secure interrupt */
681 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
682 /* global non-secure fault */
683 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
684 /* combined non-secure interrupt */
685 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
686 /* performance counter interrupts 0-7 */
687 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
689 /* per context interrupt, 64 interrupts */
690 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
Michael Walle575205c2021-10-13 18:14:13 +0200722 };
Michael Wallef3f41f62021-10-13 18:14:14 +0200723
Michael Walle7f900ea2021-10-13 18:14:26 +0200724 crypto: crypto@8000000 {
725 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
726 fsl,sec-era = <10>;
727 #address-cells = <1>;
728 #size-cells = <1>;
729 ranges = <0x0 0x00 0x8000000 0x100000>;
730 reg = <0x00 0x8000000 0x0 0x100000>;
731 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
732 dma-coherent;
733
734 sec_jr0: jr@10000 {
735 compatible = "fsl,sec-v5.0-job-ring",
736 "fsl,sec-v4.0-job-ring";
737 reg = <0x10000 0x10000>;
738 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
739 };
740
741 sec_jr1: jr@20000 {
742 compatible = "fsl,sec-v5.0-job-ring",
743 "fsl,sec-v4.0-job-ring";
744 reg = <0x20000 0x10000>;
745 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
746 };
747
748 sec_jr2: jr@30000 {
749 compatible = "fsl,sec-v5.0-job-ring",
750 "fsl,sec-v4.0-job-ring";
751 reg = <0x30000 0x10000>;
752 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
753 };
754
755 sec_jr3: jr@40000 {
756 compatible = "fsl,sec-v5.0-job-ring",
757 "fsl,sec-v4.0-job-ring";
758 reg = <0x40000 0x10000>;
759 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
760 };
761 };
762
763 qdma: dma-controller@8380000 {
764 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
765 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
766 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
767 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
768 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
773 interrupt-names = "qdma-error", "qdma-queue0",
774 "qdma-queue1", "qdma-queue2", "qdma-queue3";
775 dma-channels = <8>;
776 block-number = <1>;
777 block-offset = <0x10000>;
778 fsl,dma-queues = <2>;
779 status-sizes = <64>;
780 queue-sizes = <64 64>;
781 };
782
783 cluster1_core0_watchdog: watchdog@c000000 {
784 compatible = "arm,sp805", "arm,primecell";
785 reg = <0x0 0xc000000 0x0 0x1000>;
786 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
787 QORIQ_CLK_PLL_DIV(16)>,
788 <&clockgen QORIQ_CLK_PLATFORM_PLL
789 QORIQ_CLK_PLL_DIV(16)>;
790 clock-names = "wdog_clk", "apb_pclk";
791 };
792
793 cluster1_core1_watchdog: watchdog@c010000 {
794 compatible = "arm,sp805", "arm,primecell";
795 reg = <0x0 0xc010000 0x0 0x1000>;
796 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
797 QORIQ_CLK_PLL_DIV(16)>,
798 <&clockgen QORIQ_CLK_PLATFORM_PLL
799 QORIQ_CLK_PLL_DIV(16)>;
800 clock-names = "wdog_clk", "apb_pclk";
801 };
802
803 sai1: audio-controller@f100000 {
804 #sound-dai-cells = <0>;
805 compatible = "fsl,vf610-sai";
806 reg = <0x0 0xf100000 0x0 0x10000>;
807 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
809 QORIQ_CLK_PLL_DIV(2)>,
810 <&clockgen QORIQ_CLK_PLATFORM_PLL
811 QORIQ_CLK_PLL_DIV(2)>,
812 <&clockgen QORIQ_CLK_PLATFORM_PLL
813 QORIQ_CLK_PLL_DIV(2)>,
814 <&clockgen QORIQ_CLK_PLATFORM_PLL
815 QORIQ_CLK_PLL_DIV(2)>;
816 clock-names = "bus", "mclk1", "mclk2", "mclk3";
817 dma-names = "tx", "rx";
818 dmas = <&edma0 1 4>,
819 <&edma0 1 3>;
820 fsl,sai-asynchronous;
821 status = "disabled";
822 };
823
824 sai2: audio-controller@f110000 {
825 #sound-dai-cells = <0>;
826 compatible = "fsl,vf610-sai";
827 reg = <0x0 0xf110000 0x0 0x10000>;
828 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
830 QORIQ_CLK_PLL_DIV(2)>,
831 <&clockgen QORIQ_CLK_PLATFORM_PLL
832 QORIQ_CLK_PLL_DIV(2)>,
833 <&clockgen QORIQ_CLK_PLATFORM_PLL
834 QORIQ_CLK_PLL_DIV(2)>,
835 <&clockgen QORIQ_CLK_PLATFORM_PLL
836 QORIQ_CLK_PLL_DIV(2)>;
837 clock-names = "bus", "mclk1", "mclk2", "mclk3";
838 dma-names = "tx", "rx";
839 dmas = <&edma0 1 6>,
840 <&edma0 1 5>;
841 fsl,sai-asynchronous;
842 status = "disabled";
843 };
844
845 sai3: audio-controller@f120000 {
846 #sound-dai-cells = <0>;
847 compatible = "fsl,vf610-sai";
848 reg = <0x0 0xf120000 0x0 0x10000>;
849 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
851 QORIQ_CLK_PLL_DIV(2)>,
852 <&clockgen QORIQ_CLK_PLATFORM_PLL
853 QORIQ_CLK_PLL_DIV(2)>,
854 <&clockgen QORIQ_CLK_PLATFORM_PLL
855 QORIQ_CLK_PLL_DIV(2)>,
856 <&clockgen QORIQ_CLK_PLATFORM_PLL
857 QORIQ_CLK_PLL_DIV(2)>;
858 clock-names = "bus", "mclk1", "mclk2", "mclk3";
859 dma-names = "tx", "rx";
860 dmas = <&edma0 1 8>,
861 <&edma0 1 7>;
862 fsl,sai-asynchronous;
863 status = "disabled";
864 };
865
866 sai4: audio-controller@f130000 {
867 #sound-dai-cells = <0>;
868 compatible = "fsl,vf610-sai";
869 reg = <0x0 0xf130000 0x0 0x10000>;
870 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
872 QORIQ_CLK_PLL_DIV(2)>,
873 <&clockgen QORIQ_CLK_PLATFORM_PLL
874 QORIQ_CLK_PLL_DIV(2)>,
875 <&clockgen QORIQ_CLK_PLATFORM_PLL
876 QORIQ_CLK_PLL_DIV(2)>,
877 <&clockgen QORIQ_CLK_PLATFORM_PLL
878 QORIQ_CLK_PLL_DIV(2)>;
879 clock-names = "bus", "mclk1", "mclk2", "mclk3";
880 dma-names = "tx", "rx";
881 dmas = <&edma0 1 10>,
882 <&edma0 1 9>;
883 fsl,sai-asynchronous;
884 status = "disabled";
885 };
886
887 sai5: audio-controller@f140000 {
888 #sound-dai-cells = <0>;
889 compatible = "fsl,vf610-sai";
890 reg = <0x0 0xf140000 0x0 0x10000>;
891 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
892 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
893 QORIQ_CLK_PLL_DIV(2)>,
894 <&clockgen QORIQ_CLK_PLATFORM_PLL
895 QORIQ_CLK_PLL_DIV(2)>,
896 <&clockgen QORIQ_CLK_PLATFORM_PLL
897 QORIQ_CLK_PLL_DIV(2)>,
898 <&clockgen QORIQ_CLK_PLATFORM_PLL
899 QORIQ_CLK_PLL_DIV(2)>;
900 clock-names = "bus", "mclk1", "mclk2", "mclk3";
901 dma-names = "tx", "rx";
902 dmas = <&edma0 1 12>,
903 <&edma0 1 11>;
904 fsl,sai-asynchronous;
905 status = "disabled";
906 };
907
908 sai6: audio-controller@f150000 {
909 #sound-dai-cells = <0>;
910 compatible = "fsl,vf610-sai";
911 reg = <0x0 0xf150000 0x0 0x10000>;
912 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
914 QORIQ_CLK_PLL_DIV(2)>,
915 <&clockgen QORIQ_CLK_PLATFORM_PLL
916 QORIQ_CLK_PLL_DIV(2)>,
917 <&clockgen QORIQ_CLK_PLATFORM_PLL
918 QORIQ_CLK_PLL_DIV(2)>,
919 <&clockgen QORIQ_CLK_PLATFORM_PLL
920 QORIQ_CLK_PLL_DIV(2)>;
921 clock-names = "bus", "mclk1", "mclk2", "mclk3";
922 dma-names = "tx", "rx";
923 dmas = <&edma0 1 14>,
924 <&edma0 1 13>;
925 fsl,sai-asynchronous;
926 status = "disabled";
927 };
928
929 tmu: tmu@1f80000 {
930 compatible = "fsl,qoriq-tmu";
931 reg = <0x0 0x1f80000 0x0 0x10000>;
932 interrupts = <0 23 0x4>;
933 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
934 fsl,tmu-calibration = <0x00000000 0x00000024
935 0x00000001 0x0000002b
936 0x00000002 0x00000031
937 0x00000003 0x00000038
938 0x00000004 0x0000003f
939 0x00000005 0x00000045
940 0x00000006 0x0000004c
941 0x00000007 0x00000053
942 0x00000008 0x00000059
943 0x00000009 0x00000060
944 0x0000000a 0x00000066
945 0x0000000b 0x0000006d
946
947 0x00010000 0x0000001c
948 0x00010001 0x00000024
949 0x00010002 0x0000002c
950 0x00010003 0x00000035
951 0x00010004 0x0000003d
952 0x00010005 0x00000045
953 0x00010006 0x0000004d
954 0x00010007 0x00000055
955 0x00010008 0x0000005e
956 0x00010009 0x00000066
957 0x0001000a 0x0000006e
958
959 0x00020000 0x00000018
960 0x00020001 0x00000022
961 0x00020002 0x0000002d
962 0x00020003 0x00000038
963 0x00020004 0x00000043
964 0x00020005 0x0000004d
965 0x00020006 0x00000058
966 0x00020007 0x00000063
967 0x00020008 0x0000006e
968
969 0x00030000 0x00000010
970 0x00030001 0x0000001c
971 0x00030002 0x00000029
972 0x00030003 0x00000036
973 0x00030004 0x00000042
974 0x00030005 0x0000004f
975 0x00030006 0x0000005b
976 0x00030007 0x00000068>;
977 little-endian;
978 #thermal-sensor-cells = <1>;
979 };
980
981 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
Michael Wallef3f41f62021-10-13 18:14:14 +0200982 compatible = "pci-host-ecam-generic";
Michael Wallef3f41f62021-10-13 18:14:14 +0200983 reg = <0x01 0xf0000000 0x0 0x100000>;
984 #address-cells = <3>;
985 #size-cells = <2>;
Michael Walle7f900ea2021-10-13 18:14:26 +0200986 msi-parent = <&its>;
Michael Wallef3f41f62021-10-13 18:14:14 +0200987 device_type = "pci";
Michael Walle7f900ea2021-10-13 18:14:26 +0200988 bus-range = <0x0 0x0>;
989 dma-coherent;
990 msi-map = <0 &its 0x17 0xe>;
991 iommu-map = <0 &smmu 0x17 0xe>;
992 /* PF0-6 BAR0 - non-prefetchable memory */
993 ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
994 /* PF0-6 BAR2 - prefetchable memory */
995 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
996 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
997 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
998 /* PF0: VF0-1 BAR2 - prefetchable memory */
999 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
1000 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
1001 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
1002 /* PF1: VF0-1 BAR2 - prefetchable memory */
1003 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
1004 /* BAR4 (PF5) - non-prefetchable memory */
1005 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
Michael Wallef3f41f62021-10-13 18:14:14 +02001006
Michael Walle7f900ea2021-10-13 18:14:26 +02001007 enetc_port0: ethernet@0,0 {
1008 compatible = "fsl,enetc";
Michael Wallef3f41f62021-10-13 18:14:14 +02001009 reg = <0x000000 0 0 0 0>;
1010 status = "disabled";
1011 };
1012
Michael Walle7f900ea2021-10-13 18:14:26 +02001013 enetc_port1: ethernet@0,1 {
1014 compatible = "fsl,enetc";
Michael Wallef3f41f62021-10-13 18:14:14 +02001015 reg = <0x000100 0 0 0 0>;
1016 status = "disabled";
1017 };
1018
Michael Walle7f900ea2021-10-13 18:14:26 +02001019 enetc_port2: ethernet@0,2 {
1020 compatible = "fsl,enetc";
Michael Wallef3f41f62021-10-13 18:14:14 +02001021 reg = <0x000200 0 0 0 0>;
Michael Wallef3f41f62021-10-13 18:14:14 +02001022 phy-mode = "internal";
Michael Walle7f900ea2021-10-13 18:14:26 +02001023 status = "disabled";
Michael Wallef3f41f62021-10-13 18:14:14 +02001024
1025 fixed-link {
1026 speed = <2500>;
1027 full-duplex;
1028 };
1029 };
1030
Michael Walle7f900ea2021-10-13 18:14:26 +02001031 enetc_mdio_pf3: mdio@0,3 {
1032 compatible = "fsl,enetc-mdio";
Michael Wallef3f41f62021-10-13 18:14:14 +02001033 reg = <0x000300 0 0 0 0>;
Michael Walle7f900ea2021-10-13 18:14:26 +02001034 #address-cells = <1>;
1035 #size-cells = <0>;
Michael Wallef3f41f62021-10-13 18:14:14 +02001036 };
1037
Michael Walle7f900ea2021-10-13 18:14:26 +02001038 ethernet@0,4 {
1039 compatible = "fsl,enetc-ptp";
1040 reg = <0x000400 0 0 0 0>;
1041 clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
1042 little-endian;
1043 fsl,extts-fifo;
1044 };
1045
1046 mscc_felix: ethernet-switch@0,5 {
Michael Wallef3f41f62021-10-13 18:14:14 +02001047 reg = <0x000500 0 0 0 0>;
Michael Walle7f900ea2021-10-13 18:14:26 +02001048 /* IEP INT_B */
1049 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
Michael Wallef3f41f62021-10-13 18:14:14 +02001050 status = "disabled";
1051
1052 ports {
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055
Michael Walle7f900ea2021-10-13 18:14:26 +02001056 /* External ports */
Michael Wallef3f41f62021-10-13 18:14:14 +02001057 mscc_felix_port0: port@0 {
1058 reg = <0>;
1059 status = "disabled";
1060 };
1061
1062 mscc_felix_port1: port@1 {
1063 reg = <1>;
1064 status = "disabled";
1065 };
1066
1067 mscc_felix_port2: port@2 {
1068 reg = <2>;
1069 status = "disabled";
1070 };
1071
1072 mscc_felix_port3: port@3 {
1073 reg = <3>;
1074 status = "disabled";
1075 };
1076
Michael Walle7f900ea2021-10-13 18:14:26 +02001077 /* Internal ports */
Michael Wallef3f41f62021-10-13 18:14:14 +02001078 mscc_felix_port4: port@4 {
1079 reg = <4>;
1080 phy-mode = "internal";
1081 status = "disabled";
1082
1083 fixed-link {
1084 speed = <2500>;
1085 full-duplex;
1086 };
1087 };
1088
1089 mscc_felix_port5: port@5 {
1090 reg = <5>;
1091 phy-mode = "internal";
1092 status = "disabled";
1093
1094 fixed-link {
1095 speed = <1000>;
1096 full-duplex;
1097 };
Michael Wallef3f41f62021-10-13 18:14:14 +02001098 };
1099 };
1100 };
1101
Michael Walle7f900ea2021-10-13 18:14:26 +02001102 enetc_port3: ethernet@0,6 {
1103 compatible = "fsl,enetc";
Michael Wallef3f41f62021-10-13 18:14:14 +02001104 reg = <0x000600 0 0 0 0>;
Michael Wallef3f41f62021-10-13 18:14:14 +02001105 phy-mode = "internal";
Michael Walle7f900ea2021-10-13 18:14:26 +02001106 status = "disabled";
1107
1108 fixed-link {
1109 speed = <1000>;
1110 full-duplex;
1111 };
1112 };
1113
1114 rcec@1f,0 {
1115 reg = <0x00f800 0 0 0 0>;
1116 /* IEP INT_A */
1117 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1118 };
1119 };
1120
1121 /* Integrated Endpoint Register Block */
1122 ierb@1f0800000 {
1123 compatible = "fsl,ls1028a-enetc-ierb";
1124 reg = <0x01 0xf0800000 0x0 0x10000>;
1125 };
1126
1127 rcpm: power-controller@1e34040 {
1128 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
1129 reg = <0x0 0x1e34040 0x0 0x1c>;
1130 #fsl,rcpm-wakeup-cells = <7>;
1131 little-endian;
1132 };
1133
1134 ftm_alarm0: timer@2800000 {
1135 compatible = "fsl,ls1028a-ftm-alarm";
1136 reg = <0x0 0x2800000 0x0 0x10000>;
1137 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1138 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1139 };
1140 };
1141
1142 malidp0: display@f080000 {
1143 compatible = "arm,mali-dp500";
1144 reg = <0x0 0xf080000 0x0 0x10000>;
1145 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1146 <0 223 IRQ_TYPE_LEVEL_HIGH>;
1147 interrupt-names = "DE", "SE";
1148 clocks = <&dpclk>,
1149 <&clockgen QORIQ_CLK_HWACCEL 2>,
1150 <&clockgen QORIQ_CLK_HWACCEL 2>,
1151 <&clockgen QORIQ_CLK_HWACCEL 2>;
1152 clock-names = "pxlclk", "mclk", "aclk", "pclk";
1153 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
1154 arm,malidp-arqos-value = <0xd000d000>;
1155
1156 port {
1157 dp0_out: endpoint {
1158
Michael Wallef3f41f62021-10-13 18:14:14 +02001159 };
1160 };
Michael Wallecd80d5d2021-10-13 18:14:03 +02001161 };
Yuantian Tangd4ad1112019-04-10 16:43:33 +08001162};