blob: 56e1293720c4f1e85dd3e30819a85f8f25e98c3a [file] [log] [blame]
York Sunee52b182012-10-11 07:13:37 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
York Sunee52b182012-10-11 07:13:37 +00005 */
6
7/*
8 * T4240 QDS board configuration file
9 */
York Sun1cb19fb2013-06-27 10:48:29 -070010#ifndef __CONFIG_H
11#define __CONFIG_H
12
York Sunee52b182012-10-11 07:13:37 +000013#define CONFIG_T4240QDS
14#define CONFIG_PHYS_64BIT
York Sunee52b182012-10-11 07:13:37 +000015
16#define CONFIG_FSL_SATA_V2
17#define CONFIG_PCIE4
18
19#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20
York Sun1cb19fb2013-06-27 10:48:29 -070021#ifdef CONFIG_RAMBOOT_PBL
22#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
23#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090024#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg
25#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_rcw.cfg
York Sun1cb19fb2013-06-27 10:48:29 -070026#endif
27
28#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
29/* Set 1M boot space */
30#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
31#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
32 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
33#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
34#define CONFIG_SYS_NO_FLASH
35#endif
36
37#define CONFIG_SRIO_PCIE_BOOT_MASTER
38#define CONFIG_DDR_ECC
39
York Sunee52b182012-10-11 07:13:37 +000040#include "t4qds.h"
York Sun1cb19fb2013-06-27 10:48:29 -070041
42#ifdef CONFIG_SYS_NO_FLASH
43#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
44#define CONFIG_ENV_IS_NOWHERE
45#endif
46#else
47#define CONFIG_FLASH_CFI_DRIVER
48#define CONFIG_SYS_FLASH_CFI
49#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
50#endif
51
52#if defined(CONFIG_SPIFLASH)
53#define CONFIG_SYS_EXTRA_ENV_RELOC
54#define CONFIG_ENV_IS_IN_SPI_FLASH
55#define CONFIG_ENV_SPI_BUS 0
56#define CONFIG_ENV_SPI_CS 0
57#define CONFIG_ENV_SPI_MAX_HZ 10000000
58#define CONFIG_ENV_SPI_MODE 0
59#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
60#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
61#define CONFIG_ENV_SECT_SIZE 0x10000
62#elif defined(CONFIG_SDCARD)
63#define CONFIG_SYS_EXTRA_ENV_RELOC
64#define CONFIG_ENV_IS_IN_MMC
65#define CONFIG_SYS_MMC_ENV_DEV 0
66#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053067#define CONFIG_ENV_OFFSET (512 * 1658)
York Sun1cb19fb2013-06-27 10:48:29 -070068#elif defined(CONFIG_NAND)
69#define CONFIG_SYS_EXTRA_ENV_RELOC
70#define CONFIG_ENV_IS_IN_NAND
71#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053072#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
York Sun1cb19fb2013-06-27 10:48:29 -070073#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
74#define CONFIG_ENV_IS_IN_REMOTE
75#define CONFIG_ENV_ADDR 0xffe20000
76#define CONFIG_ENV_SIZE 0x2000
77#elif defined(CONFIG_ENV_IS_NOWHERE)
78#define CONFIG_ENV_SIZE 0x2000
79#else
80#define CONFIG_ENV_IS_IN_FLASH
81#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
82#define CONFIG_ENV_SIZE 0x2000
83#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
84#endif
85
86#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
87#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
88
89#ifndef __ASSEMBLY__
90unsigned long get_board_sys_clk(void);
91unsigned long get_board_ddr_clk(void);
92#endif
93
94/* EEPROM */
95#define CONFIG_ID_EEPROM
96#define CONFIG_SYS_I2C_EEPROM_NXID
97#define CONFIG_SYS_EEPROM_BUS_NUM 0
98#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
99#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
100
101/*
102 * DDR Setup
103 */
104#define CONFIG_SYS_SPD_BUS_NUM 0
105#define SPD_EEPROM_ADDRESS1 0x51
106#define SPD_EEPROM_ADDRESS2 0x52
107#define SPD_EEPROM_ADDRESS3 0x53
108#define SPD_EEPROM_ADDRESS4 0x54
109#define SPD_EEPROM_ADDRESS5 0x55
110#define SPD_EEPROM_ADDRESS6 0x56
111#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
112#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
113
114/*
115 * IFC Definitions
116 */
117#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
118#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
119 + 0x8000000) | \
120 CSPR_PORT_SIZE_16 | \
121 CSPR_MSEL_NOR | \
122 CSPR_V)
123#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
124#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
125 CSPR_PORT_SIZE_16 | \
126 CSPR_MSEL_NOR | \
127 CSPR_V)
128#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
129/* NOR Flash Timing Params */
130#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
131
132#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
133 FTIM0_NOR_TEADC(0x5) | \
134 FTIM0_NOR_TEAHC(0x5))
135#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
136 FTIM1_NOR_TRAD_NOR(0x1A) |\
137 FTIM1_NOR_TSEQRAD_NOR(0x13))
138#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
139 FTIM2_NOR_TCH(0x4) | \
140 FTIM2_NOR_TWPH(0x0E) | \
141 FTIM2_NOR_TWP(0x1c))
142#define CONFIG_SYS_NOR_FTIM3 0x0
143
144#define CONFIG_SYS_FLASH_QUIET_TEST
145#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
146
147#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
148#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
149#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
150#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
151
152#define CONFIG_SYS_FLASH_EMPTY_INFO
153#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
154 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
155
156#define CONFIG_FSL_QIXIS /* use common QIXIS code */
157#define QIXIS_BASE 0xffdf0000
158#define QIXIS_LBMAP_SWITCH 6
159#define QIXIS_LBMAP_MASK 0x0f
160#define QIXIS_LBMAP_SHIFT 0
161#define QIXIS_LBMAP_DFLTBANK 0x00
162#define QIXIS_LBMAP_ALTBANK 0x04
163#define QIXIS_RST_CTL_RESET 0x83
York Sunc63e1372013-06-25 11:37:48 -0700164#define QIXIS_RST_FORCE_MEM 0x1
York Sun1cb19fb2013-06-27 10:48:29 -0700165#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
166#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
167#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Haijun.Zhangf7e27cc2014-01-10 13:52:17 +0800168#define QIXIS_BRDCFG5 0x55
169#define QIXIS_MUX_SDHC 2
Haijun.Zhangd47e3d22014-01-10 13:52:18 +0800170#define QIXIS_MUX_SDHC_WIDTH8 1
York Sun1cb19fb2013-06-27 10:48:29 -0700171#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
172
173#define CONFIG_SYS_CSPR3_EXT (0xf)
174#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
175 | CSPR_PORT_SIZE_8 \
176 | CSPR_MSEL_GPCM \
177 | CSPR_V)
178#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
179#define CONFIG_SYS_CSOR3 0x0
180/* QIXIS Timing parameters for IFC CS3 */
181#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
182 FTIM0_GPCM_TEADC(0x0e) | \
183 FTIM0_GPCM_TEAHC(0x0e))
184#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
185 FTIM1_GPCM_TRAD(0x3f))
186#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
187 FTIM2_GPCM_TCH(0x0) | \
188 FTIM2_GPCM_TWP(0x1f))
189#define CONFIG_SYS_CS3_FTIM3 0x0
190
191/* NAND Flash on IFC */
192#define CONFIG_NAND_FSL_IFC
193#define CONFIG_SYS_NAND_BASE 0xff800000
194#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
195
196#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
197#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
198 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
199 | CSPR_MSEL_NAND /* MSEL = NAND */ \
200 | CSPR_V)
201#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
202
203#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
204 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
205 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
206 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
207 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
208 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
209 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
210
211#define CONFIG_SYS_NAND_ONFI_DETECTION
212
213/* ONFI NAND Flash mode0 Timing Params */
214#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
215 FTIM0_NAND_TWP(0x18) | \
216 FTIM0_NAND_TWCHT(0x07) | \
217 FTIM0_NAND_TWH(0x0a))
218#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
219 FTIM1_NAND_TWBE(0x39) | \
220 FTIM1_NAND_TRR(0x0e) | \
221 FTIM1_NAND_TRP(0x18))
222#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
223 FTIM2_NAND_TREH(0x0a) | \
224 FTIM2_NAND_TWHRE(0x1e))
225#define CONFIG_SYS_NAND_FTIM3 0x0
226
227#define CONFIG_SYS_NAND_DDR_LAW 11
228
229#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
230#define CONFIG_SYS_MAX_NAND_DEVICE 1
231#define CONFIG_MTD_NAND_VERIFY_WRITE
232#define CONFIG_CMD_NAND
233
234#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Prabhakar Kushwaha68ec9c82013-10-04 13:47:58 +0530235#define CONFIG_SYS_NAND_MAX_OOBFREE 2
236#define CONFIG_SYS_NAND_MAX_ECCPOS 256
York Sun1cb19fb2013-06-27 10:48:29 -0700237
238#if defined(CONFIG_NAND)
239#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
240#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
241#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
242#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
243#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
244#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
245#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
246#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
247#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
248#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
249#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
250#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
251#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
252#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
253#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
254#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
255#else
256#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
257#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
258#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
259#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
260#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
261#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
262#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
263#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
264#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
265#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
266#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
267#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
268#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
269#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
270#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
271#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
272#endif
273#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
274#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
275#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
276#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
277#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
278#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
279#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
280#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
281
282#if defined(CONFIG_RAMBOOT_PBL)
283#define CONFIG_SYS_RAMBOOT
284#endif
285
286
287/* I2C */
288#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
289#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
290#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
291#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
292
293#define I2C_MUX_CH_DEFAULT 0x8
294#define I2C_MUX_CH_VOL_MONITOR 0xa
295#define I2C_MUX_CH_VSC3316_FS 0xc
296#define I2C_MUX_CH_VSC3316_BS 0xd
297
298/* Voltage monitor on channel 2*/
299#define I2C_VOL_MONITOR_ADDR 0x40
300#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
301#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
302#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
303
304/* VSC Crossbar switches */
305#define CONFIG_VSC_CROSSBAR
306#define VSC3316_FSM_TX_ADDR 0x70
307#define VSC3316_FSM_RX_ADDR 0x71
308
309/*
310 * RapidIO
311 */
312
313/*
314 * for slave u-boot IMAGE instored in master memory space,
315 * PHYS must be aligned based on the SIZE
316 */
317#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
318#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
319#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
320#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
321/*
322 * for slave UCODE and ENV instored in master memory space,
323 * PHYS must be aligned based on the SIZE
324 */
325#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
326#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
327#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
328
329/* slave core release by master*/
330#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
331#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
332
333/*
334 * SRIO_PCIE_BOOT - SLAVE
335 */
336#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
337#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
338#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
339 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
340#endif
341/*
342 * eSPI - Enhanced SPI
343 */
344#define CONFIG_FSL_ESPI
345#define CONFIG_SPI_FLASH
346#define CONFIG_SPI_FLASH_SST
347#define CONFIG_CMD_SF
348#define CONFIG_SF_DEFAULT_SPEED 10000000
349#define CONFIG_SF_DEFAULT_MODE 0
350
351
352/* Qman/Bman */
353#ifndef CONFIG_NOBQFMAN
354#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
355#define CONFIG_SYS_BMAN_NUM_PORTALS 50
356#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
357#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
358#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
359#define CONFIG_SYS_QMAN_NUM_PORTALS 50
360#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
361#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
362#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
363
364#define CONFIG_SYS_DPAA_FMAN
365#define CONFIG_SYS_DPAA_PME
366#define CONFIG_SYS_PMAN
367#define CONFIG_SYS_DPAA_DCE
Minghuan Lian0795eff2013-07-03 18:32:41 +0800368#define CONFIG_SYS_DPAA_RMAN
York Sun1cb19fb2013-06-27 10:48:29 -0700369#define CONFIG_SYS_INTERLAKEN
370
371/* Default address of microcode for the Linux Fman driver */
372#if defined(CONFIG_SPIFLASH)
373/*
374 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
375 * env, so we got 0x110000.
376 */
377#define CONFIG_SYS_QE_FW_IN_SPIFLASH
378#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
379#elif defined(CONFIG_SDCARD)
380/*
381 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530382 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
383 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
York Sun1cb19fb2013-06-27 10:48:29 -0700384 */
385#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530386#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
York Sun1cb19fb2013-06-27 10:48:29 -0700387#elif defined(CONFIG_NAND)
388#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530389#define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
York Sun1cb19fb2013-06-27 10:48:29 -0700390#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
391/*
392 * Slave has no ucode locally, it can fetch this from remote. When implementing
393 * in two corenet boards, slave's ucode could be stored in master's memory
394 * space, the address can be mapped from slave TLB->slave LAW->
395 * slave SRIO or PCIE outbound window->master inbound window->
396 * master LAW->the ucode address in master's memory space.
397 */
398#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
399#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
400#else
401#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530402#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
York Sun1cb19fb2013-06-27 10:48:29 -0700403#endif
404#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
405#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
406#endif /* CONFIG_NOBQFMAN */
407
408#ifdef CONFIG_SYS_DPAA_FMAN
409#define CONFIG_FMAN_ENET
410#define CONFIG_PHYLIB_10G
411#define CONFIG_PHY_VITESSE
412#define CONFIG_PHY_TERANETICS
413#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
414#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
415#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
416#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
417#define FM1_10GEC1_PHY_ADDR 0x0
418#define FM1_10GEC2_PHY_ADDR 0x1
419#define FM2_10GEC1_PHY_ADDR 0x2
420#define FM2_10GEC2_PHY_ADDR 0x3
421#endif
422
423
424/* SATA */
425#ifdef CONFIG_FSL_SATA_V2
426#define CONFIG_LIBATA
427#define CONFIG_FSL_SATA
428
429#define CONFIG_SYS_SATA_MAX_DEVICE 2
430#define CONFIG_SATA1
431#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
432#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
433#define CONFIG_SATA2
434#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
435#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
436
437#define CONFIG_LBA48
438#define CONFIG_CMD_SATA
439#define CONFIG_DOS_PARTITION
440#define CONFIG_CMD_EXT2
441#endif
442
443#ifdef CONFIG_FMAN_ENET
444#define CONFIG_MII /* MII PHY management */
445#define CONFIG_ETHPRIME "FM1@DTSEC1"
446#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
447#endif
448
449/*
450* USB
451*/
452#define CONFIG_CMD_USB
453#define CONFIG_USB_STORAGE
454#define CONFIG_USB_EHCI
455#define CONFIG_USB_EHCI_FSL
456#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
457#define CONFIG_CMD_EXT2
458#define CONFIG_HAS_FSL_DR_USB
459
460#define CONFIG_MMC
461
462#ifdef CONFIG_MMC
463#define CONFIG_FSL_ESDHC
464#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
465#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
466#define CONFIG_CMD_MMC
467#define CONFIG_GENERIC_MMC
468#define CONFIG_CMD_EXT2
469#define CONFIG_CMD_FAT
470#define CONFIG_DOS_PARTITION
Haijun.Zhangef38f3f2013-10-31 09:38:19 +0800471#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Haijun.Zhangf7e27cc2014-01-10 13:52:17 +0800472#define CONFIG_ESDHC_DETECT_QUIRK \
473 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
474 IS_SVR_REV(get_svr(), 1, 0))
Haijun.Zhangd47e3d22014-01-10 13:52:18 +0800475#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
476 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
York Sun1cb19fb2013-06-27 10:48:29 -0700477#endif
478
479#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
480
481#define __USB_PHY_TYPE utmi
482
483/*
484 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
485 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
486 * interleaving. It can be cacheline, page, bank, superbank.
487 * See doc/README.fsl-ddr for details.
488 */
489#ifdef CONFIG_PPC_T4240
490#define CTRL_INTLV_PREFERED 3way_4KB
491#else
492#define CTRL_INTLV_PREFERED cacheline
493#endif
494
495#define CONFIG_EXTRA_ENV_SETTINGS \
496 "hwconfig=fsl_ddr:" \
497 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
498 "bank_intlv=auto;" \
499 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
500 "netdev=eth0\0" \
501 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
502 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
503 "tftpflash=tftpboot $loadaddr $uboot && " \
504 "protect off $ubootaddr +$filesize && " \
505 "erase $ubootaddr +$filesize && " \
506 "cp.b $loadaddr $ubootaddr $filesize && " \
507 "protect on $ubootaddr +$filesize && " \
508 "cmp.b $loadaddr $ubootaddr $filesize\0" \
509 "consoledev=ttyS0\0" \
510 "ramdiskaddr=2000000\0" \
511 "ramdiskfile=t4240qds/ramdisk.uboot\0" \
512 "fdtaddr=c00000\0" \
513 "fdtfile=t4240qds/t4240qds.dtb\0" \
514 "bdev=sda3\0" \
515 "c=ffe\0"
516
517#define CONFIG_HVBOOT \
518 "setenv bootargs config-addr=0x60000000; " \
519 "bootm 0x01000000 - 0x00f00000"
520
521#define CONFIG_ALU \
522 "setenv bootargs root=/dev/$bdev rw " \
523 "console=$consoledev,$baudrate $othbootargs;" \
524 "cpu 1 release 0x01000000 - - -;" \
525 "cpu 2 release 0x01000000 - - -;" \
526 "cpu 3 release 0x01000000 - - -;" \
527 "cpu 4 release 0x01000000 - - -;" \
528 "cpu 5 release 0x01000000 - - -;" \
529 "cpu 6 release 0x01000000 - - -;" \
530 "cpu 7 release 0x01000000 - - -;" \
531 "go 0x01000000"
532
533#define CONFIG_LINUX \
534 "setenv bootargs root=/dev/ram rw " \
535 "console=$consoledev,$baudrate $othbootargs;" \
536 "setenv ramdiskaddr 0x02000000;" \
537 "setenv fdtaddr 0x00c00000;" \
538 "setenv loadaddr 0x1000000;" \
539 "bootm $loadaddr $ramdiskaddr $fdtaddr"
540
541#define CONFIG_HDBOOT \
542 "setenv bootargs root=/dev/$bdev rw " \
543 "console=$consoledev,$baudrate $othbootargs;" \
544 "tftp $loadaddr $bootfile;" \
545 "tftp $fdtaddr $fdtfile;" \
546 "bootm $loadaddr - $fdtaddr"
547
548#define CONFIG_NFSBOOTCOMMAND \
549 "setenv bootargs root=/dev/nfs rw " \
550 "nfsroot=$serverip:$rootpath " \
551 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
552 "console=$consoledev,$baudrate $othbootargs;" \
553 "tftp $loadaddr $bootfile;" \
554 "tftp $fdtaddr $fdtfile;" \
555 "bootm $loadaddr - $fdtaddr"
556
557#define CONFIG_RAMBOOTCOMMAND \
558 "setenv bootargs root=/dev/ram rw " \
559 "console=$consoledev,$baudrate $othbootargs;" \
560 "tftp $ramdiskaddr $ramdiskfile;" \
561 "tftp $loadaddr $bootfile;" \
562 "tftp $fdtaddr $fdtfile;" \
563 "bootm $loadaddr $ramdiskaddr $fdtaddr"
564
565#define CONFIG_BOOTCOMMAND CONFIG_LINUX
566
York Sun1cb19fb2013-06-27 10:48:29 -0700567#include <asm/fsl_secure_boot.h>
York Sun1cb19fb2013-06-27 10:48:29 -0700568
569#endif /* __CONFIG_H */