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wdenk16f21702002-08-26 21:58:50 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * (C) Copyright 2001
5 * Torsten Stevens, FHG IMS, stevens@ims.fhg.de
6 * Bruno Achauer, Exet AG, bruno@exet-ag.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * Derived from ../tqm8xx/tqm8xx.c
29 */
30
31#include <common.h>
32#include <mpc8xx.h>
33
34/* ------------------------------------------------------------------------- */
35
36static long int dram_size (long int, long int *, long int);
37
38/* ------------------------------------------------------------------------- */
39
40#define _NOT_USED_ 0xFFFFFFFF
41
wdenkc83bf6a2004-01-06 22:38:14 +000042const uint sdram_table[] = {
wdenk16f21702002-08-26 21:58:50 +000043 /*
44 * Single Read. (Offset 0 in UPMA RAM)
45 */
46 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
wdenkc83bf6a2004-01-06 22:38:14 +000047 0x1ff77c47, /* last */
wdenk16f21702002-08-26 21:58:50 +000048 /*
49 * SDRAM Initialization (offset 5 in UPMA RAM)
50 *
51 * This is no UPM entry point. The following definition uses
52 * the remaining space to establish an initialization
53 * sequence, which is executed by a RUN command.
54 *
55 */
wdenkc83bf6a2004-01-06 22:38:14 +000056 0x1ff77c35, 0xefeabc34, 0x1fb57c35, /* last */
wdenk16f21702002-08-26 21:58:50 +000057 /*
58 * Burst Read. (Offset 8 in UPMA RAM)
59 */
60 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
wdenkc83bf6a2004-01-06 22:38:14 +000061 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
wdenk16f21702002-08-26 21:58:50 +000062 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 /*
65 * Single Write. (Offset 18 in UPMA RAM)
66 */
wdenkc83bf6a2004-01-06 22:38:14 +000067 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
wdenk16f21702002-08-26 21:58:50 +000068 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
69 /*
70 * Burst Write. (Offset 20 in UPMA RAM)
71 */
72 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
wdenkc83bf6a2004-01-06 22:38:14 +000073 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
74 _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +000075 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
77 /*
78 * Refresh (Offset 30 in UPMA RAM)
79 */
80 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
wdenkc83bf6a2004-01-06 22:38:14 +000081 0xfffffc84, 0xfffffc07, 0xfffffc07, /* last */
82 _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +000083 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 /*
85 * Exception. (Offset 3c in UPMA RAM)
86 */
wdenkc83bf6a2004-01-06 22:38:14 +000087 0x7ffffc07, /* last */
88 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +000089};
90
91/* ------------------------------------------------------------------------- */
92
93
94/*
95 * Check Board Identity:
96 *
97 * Test TQ ID string (TQM8xx...)
98 * If present, check for "L" type (no second DRAM bank),
99 * otherwise "L" type is assumed as default.
100 *
101 * Return 1 for "L" type, 0 else.
102 */
103
104int checkboard (void)
105{
wdenkc83bf6a2004-01-06 22:38:14 +0000106 printf ("Board: Lantec special edition rev.%d\n", CONFIG_LANTEC);
wdenk16f21702002-08-26 21:58:50 +0000107 return 0;
108}
109
110/* ------------------------------------------------------------------------- */
111
Becky Bruce9973e3c2008-06-09 16:03:40 -0500112phys_size_t initdram (int board_type)
wdenk16f21702002-08-26 21:58:50 +0000113{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk16f21702002-08-26 21:58:50 +0000115 volatile memctl8xx_t *memctl = &immap->im_memctl;
116 long int size_b0;
117 int i;
118
119 /*
120 * Configure UPMA for SDRAM
121 */
wdenkc83bf6a2004-01-06 22:38:14 +0000122 upmconfig (UPMA, (uint *) sdram_table,
123 sizeof (sdram_table) / sizeof (uint));
wdenk16f21702002-08-26 21:58:50 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ;
wdenk16f21702002-08-26 21:58:50 +0000126
127 /* burst length=4, burst type=sequential, CAS latency=2 */
128 memctl->memc_mar = 0x00000088;
129
130 /*
wdenkc83bf6a2004-01-06 22:38:14 +0000131 * Map controller bank 3 to the SDRAM bank at preliminary address.
132 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
134 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
wdenk16f21702002-08-26 21:58:50 +0000135
136 /* initialize memory address register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */
wdenk16f21702002-08-26 21:58:50 +0000138
139 /* mode initialization (offset 5) */
wdenkc83bf6a2004-01-06 22:38:14 +0000140 udelay (200); /* 0x80006105 */
141 memctl->memc_mcr =
142 MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
wdenk16f21702002-08-26 21:58:50 +0000143
144 /* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
wdenkc83bf6a2004-01-06 22:38:14 +0000145 udelay (1); /* 0x80006130 */
146 memctl->memc_mcr =
147 MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
148 udelay (1); /* 0x80006130 */
149 memctl->memc_mcr =
150 MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
wdenk16f21702002-08-26 21:58:50 +0000151
wdenkc83bf6a2004-01-06 22:38:14 +0000152 udelay (1); /* 0x80006106 */
153 memctl->memc_mcr =
154 MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
wdenk16f21702002-08-26 21:58:50 +0000155
wdenk2535d602003-07-17 23:16:40 +0000156 memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
wdenk16f21702002-08-26 21:58:50 +0000157
wdenkc83bf6a2004-01-06 22:38:14 +0000158 udelay (200);
wdenk16f21702002-08-26 21:58:50 +0000159
160 /* Need at least 10 DRAM accesses to stabilize */
wdenkc83bf6a2004-01-06 22:38:14 +0000161 for (i = 0; i < 10; ++i) {
162 volatile unsigned long *addr =
163 (volatile unsigned long *) SDRAM_BASE3_PRELIM;
wdenk16f21702002-08-26 21:58:50 +0000164 unsigned long val;
165
166 val = *(addr + i);
167 *(addr + i) = val;
168 }
169
170 /*
wdenkc83bf6a2004-01-06 22:38:14 +0000171 * Check Bank 0 Memory Size for re-configuration
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 size_b0 = dram_size (CONFIG_SYS_MAMR_8COL,
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200174 (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
wdenk16f21702002-08-26 21:58:50 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
wdenk16f21702002-08-26 21:58:50 +0000177
178 /*
179 * Final mapping:
180 */
181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
183 memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkc83bf6a2004-01-06 22:38:14 +0000184 udelay (1000);
wdenk16f21702002-08-26 21:58:50 +0000185
186 return (size_b0);
187}
188
189/* ------------------------------------------------------------------------- */
190
191/*
192 * Check memory range for valid RAM. A simple memory test determines
193 * the actually available RAM size between addresses `base' and
194 * `base + maxsize'. Some (not all) hardware errors are detected:
195 * - short between address lines
196 * - short between data lines
197 */
198
wdenkc83bf6a2004-01-06 22:38:14 +0000199static long int dram_size (long int mamr_value, long int *base,
200 long int maxsize)
wdenk16f21702002-08-26 21:58:50 +0000201{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkc83bf6a2004-01-06 22:38:14 +0000203 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk16f21702002-08-26 21:58:50 +0000204
wdenkc83bf6a2004-01-06 22:38:14 +0000205 memctl->memc_mamr = mamr_value;
wdenk16f21702002-08-26 21:58:50 +0000206
wdenkc83bf6a2004-01-06 22:38:14 +0000207 return (get_ram_size (base, maxsize));
wdenk16f21702002-08-26 21:58:50 +0000208}