blob: 478d0d8f9d300e0950a0656e7d5242e75bc12213 [file] [log] [blame]
Paul Gortmaker91e25762007-01-16 11:38:14 -05001/*
2 * WindRiver SBC8349 U-Boot configuration file.
3 * Copyright (c) 2006, 2007 Wind River Systems, Inc.
4 *
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on the MPC8349EMDS config.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * sbc8349 board configuration file.
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
Paul Gortmaker91e25762007-01-16 11:38:14 -050034/*
35 * High Level Configuration Options
36 */
37#define CONFIG_E300 1 /* E300 Family */
Peter Tyser0f898602009-05-22 17:23:24 -050038#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050039#define CONFIG_MPC834x 1 /* MPC834x family */
Paul Gortmaker91e25762007-01-16 11:38:14 -050040#define CONFIG_MPC8349 1 /* MPC8349 specific */
41#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */
42
Wolfgang Denk2ae18242010-10-06 09:05:45 +020043#define CONFIG_SYS_TEXT_BASE 0xFF800000
44
Paul Gortmaker91e25762007-01-16 11:38:14 -050045/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
46#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
47
Paul Gortmakerc0d660f2009-08-21 16:21:58 -050048/*
49 * The default if PCI isn't enabled, or if no PCI clk setting is given
50 * is 66MHz; this is what the board defaults to when the PCI slot is
51 * physically empty. The board will automatically (i.e w/o jumpers)
52 * clock down to 33MHz if you insert a 33MHz PCI card.
53 */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020054#ifdef CONFIG_PCI_33M
Paul Gortmaker91e25762007-01-16 11:38:14 -050055#define CONFIG_83XX_CLKIN 33000000 /* in Hz */
Paul Gortmakerc0d660f2009-08-21 16:21:58 -050056#else /* 66M */
57#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
Paul Gortmaker91e25762007-01-16 11:38:14 -050058#endif
59
60#ifndef CONFIG_SYS_CLK_FREQ
Wolfgang Denk2ae18242010-10-06 09:05:45 +020061#ifdef CONFIG_PCI_33M
Paul Gortmaker91e25762007-01-16 11:38:14 -050062#define CONFIG_SYS_CLK_FREQ 33000000
63#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1
Paul Gortmakerc0d660f2009-08-21 16:21:58 -050064#else /* 66M */
65#define CONFIG_SYS_CLK_FREQ 66000000
66#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1
Paul Gortmaker91e25762007-01-16 11:38:14 -050067#endif
68#endif
69
Paul Gortmaker91e25762007-01-16 11:38:14 -050070#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
71
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_IMMR 0xE0000000
Paul Gortmaker91e25762007-01-16 11:38:14 -050073
Joe Hershberger60e1dc12011-10-11 23:57:25 -050074#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
76#define CONFIG_SYS_MEMTEST_END 0x00100000
Paul Gortmaker91e25762007-01-16 11:38:14 -050077
78/*
79 * DDR Setup
80 */
81#undef CONFIG_DDR_ECC /* only for ECC DDR module */
82#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
83#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
Joe Hershberger60e1dc12011-10-11 23:57:25 -050084#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */
Paul Gortmaker91e25762007-01-16 11:38:14 -050085
86/*
87 * 32-bit data path mode.
88 *
89 * Please note that using this mode for devices with the real density of 64-bit
90 * effectively reduces the amount of available memory due to the effect of
91 * wrapping around while translating address to row/columns, for example in the
92 * 256MB module the upper 128MB get aliased with contents of the lower
93 * 128MB); normally this define should be used for devices with real 32-bit
94 * data path.
95 */
96#undef CONFIG_DDR_32BIT
97
Joe Hershberger60e1dc12011-10-11 23:57:25 -050098#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
100#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
101#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500102 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
103#define CONFIG_DDR_2T_TIMING
104
105#if defined(CONFIG_SPD_EEPROM)
106/*
107 * Determine DDR configuration from I2C interface.
108 */
109#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
110
111#else
112/*
113 * Manually set up DDR parameters
114 * NB: manual DDR setup untested on sbc834x
115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershberger2e651b22011-10-11 23:57:31 -0500117#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500118 | CSCONFIG_ROW_BIT_13 \
119 | CSCONFIG_COL_BIT_10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_DDR_TIMING_1 0x36332321
121#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500122#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500124
125#if defined(CONFIG_DDR_32BIT)
126/* set burst length to 8 for 32-bit data path */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500127 /* DLL,normal,seq,4/2.5, 8 burst len */
128#define CONFIG_SYS_DDR_MODE 0x00000023
Paul Gortmaker91e25762007-01-16 11:38:14 -0500129#else
130/* the default burst length is 4 - for 64-bit data path */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500131 /* DLL,normal,seq,4/2.5, 4 burst len */
132#define CONFIG_SYS_DDR_MODE 0x00000022
Paul Gortmaker91e25762007-01-16 11:38:14 -0500133#endif
134#endif
135
136/*
137 * SDRAM on the Local Bus
138 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500139#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
140#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500141
142/*
143 * FLASH on the Local Bus
144 */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500145#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
146#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */
148#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
149/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500150
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500151#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
152 | BR_PS_16 /* 16 bit port */ \
153 | BR_MS_GPCM /* MSEL = GPCM */ \
154 | BR_V) /* valid */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500155
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500156#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
157 | OR_GPCM_XAM \
158 | OR_GPCM_CSNT \
159 | OR_GPCM_ACS_DIV2 \
160 | OR_GPCM_XACS \
161 | OR_GPCM_SCY_15 \
162 | OR_GPCM_TRLX_SET \
163 | OR_GPCM_EHTR_SET \
164 | OR_GPCM_EAD)
165 /* 0xFF806FF7 */
166
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500167 /* window base at flash base */
168#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500169#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500170
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500171#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
172#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#undef CONFIG_SYS_FLASH_CHECKSUM
175#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
176#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500177
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200178#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
181#define CONFIG_SYS_RAMBOOT
Paul Gortmaker91e25762007-01-16 11:38:14 -0500182#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#undef CONFIG_SYS_RAMBOOT
Paul Gortmaker91e25762007-01-16 11:38:14 -0500184#endif
185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500187 /* Initial RAM address */
188#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000
189 /* Size of used area in RAM*/
190#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500191
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500192#define CONFIG_SYS_GBL_DATA_OFFSET \
193 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Paul Gortmaker91e25762007-01-16 11:38:14 -0500195
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500196#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
Kim Phillipsc8a90642012-06-30 18:29:20 -0500197#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500198
199/*
200 * Local Bus LCRR and LBCR regs
201 * LCRR: DLL bypass, Clock divider is 4
202 * External Local Bus rate is
203 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
204 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500205#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
206#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_LBC_LBCR 0x00000000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#ifdef CONFIG_SYS_LB_SDRAM
Paul Gortmaker91e25762007-01-16 11:38:14 -0500212/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
213/*
214 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Paul Gortmaker91e25762007-01-16 11:38:14 -0500216 *
217 * For BR2, need:
218 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
219 * port-size = 32-bits = BR2[19:20] = 11
220 * no parity checking = BR2[21:22] = 00
221 * SDRAM for MSEL = BR2[24:26] = 011
222 * Valid = BR[31] = 1
223 *
224 * 0 4 8 12 16 20 24 28
225 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
Paul Gortmaker91e25762007-01-16 11:38:14 -0500226 */
227
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500228#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
229 | BR_PS_32 \
230 | BR_MS_SDRAM \
231 | BR_V)
232 /* 0xF0001861 */
233#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
234#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500235
236/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Paul Gortmaker91e25762007-01-16 11:38:14 -0500238 *
239 * For OR2, need:
240 * 64MB mask for AM, OR2[0:7] = 1111 1100
241 * XAM, OR2[17:18] = 11
242 * 9 columns OR2[19-21] = 010
243 * 13 rows OR2[23-25] = 100
244 * EAD set for extra time OR[31] = 1
245 *
246 * 0 4 8 12 16 20 24 28
247 * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
248 */
249
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500250#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
251 | OR_SDRAM_XAM \
252 | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
253 | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
254 | OR_SDRAM_EAD)
255 /* 0xFC006901 */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500256
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500257 /* LB sdram refresh timer, about 6us */
258#define CONFIG_SYS_LBC_LSRT 0x32000000
259 /* LB refresh timer prescal, 266MHz/32 */
260#define CONFIG_SYS_LBC_MRTPR 0x20000000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500261
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500262#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
263 | LSDMR_BSMA1516 \
264 | LSDMR_RFCR8 \
265 | LSDMR_PRETOACT6 \
266 | LSDMR_ACTTORW3 \
267 | LSDMR_BL8 \
268 | LSDMR_WRC3 \
269 | LSDMR_CL3)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500270
271/*
272 * SDRAM Controller configuration sequence.
273 */
Kumar Gala540dcf12009-03-26 01:34:39 -0500274#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
275#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
276#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
277#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
278#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500279#endif
280
281/*
282 * Serial Port
283 */
284#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_NS16550
286#define CONFIG_SYS_NS16550_SERIAL
287#define CONFIG_SYS_NS16550_REG_SIZE 1
288#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500291 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Paul Gortmaker91e25762007-01-16 11:38:14 -0500292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
294#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500295
Kim Phillips22d71a72007-02-27 18:41:08 -0600296#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500297#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500298/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_HUSH_PARSER
Paul Gortmaker91e25762007-01-16 11:38:14 -0500300
301/* pass open firmware flat tree */
Paul Gortmakere4968652007-12-20 12:58:51 -0500302#define CONFIG_OF_LIBFDT 1
Paul Gortmaker91e25762007-01-16 11:38:14 -0500303#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600304#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Paul Gortmaker91e25762007-01-16 11:38:14 -0500305
306/* I2C */
307#define CONFIG_HARD_I2C /* I2C with hardware support*/
308#undef CONFIG_SOFT_I2C /* I2C bit-banged */
309#define CONFIG_FSL_I2C
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500310#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
311#define CONFIG_SYS_I2C_SLAVE 0x7F
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500313#define CONFIG_SYS_I2C1_OFFSET 0x3000
314#define CONFIG_SYS_I2C2_OFFSET 0x3100
315#define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET
Paul Gortmakerefaf6f12009-10-02 18:54:20 -0400316/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500317
318/* TSEC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500320#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500322#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500323
324/*
325 * General PCI
326 * Addresses are mapped 1-1.
327 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
329#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
330#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
331#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
332#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
333#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500334#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
335#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
336#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
339#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
340#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
341#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
342#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
343#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500344#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
345#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
346#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500347
348#if defined(CONFIG_PCI)
349
350#define PCI_64BIT
351#define PCI_ONE_PCI1
352#if defined(PCI_64BIT)
353#undef PCI_ALL_PCI1
354#undef PCI_TWO_PCI1
355#undef PCI_ONE_PCI1
356#endif
357
Paul Gortmaker91e25762007-01-16 11:38:14 -0500358#define CONFIG_PCI_PNP /* do pci plug-and-play */
359
360#undef CONFIG_EEPRO100
361#undef CONFIG_TULIP
362
363#if !defined(CONFIG_PCI_PNP)
364 #define PCI_ENET0_IOADDR 0xFIXME
365 #define PCI_ENET0_MEMADDR 0xFIXME
366 #define PCI_IDSEL_NUMBER 0xFIXME
367#endif
368
369#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500371
372#endif /* CONFIG_PCI */
373
374/*
375 * TSEC configuration
376 */
377#define CONFIG_TSEC_ENET /* TSEC ethernet support */
378
379#if defined(CONFIG_TSEC_ENET)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500380
Kim Phillips255a35772007-05-16 16:52:19 -0500381#define CONFIG_TSEC1 1
382#define CONFIG_TSEC1_NAME "TSEC0"
383#define CONFIG_TSEC2 1
384#define CONFIG_TSEC2_NAME "TSEC1"
Paul Gortmaker91e25762007-01-16 11:38:14 -0500385#define CONFIG_PHY_BCM5421S 1
386#define TSEC1_PHY_ADDR 0x19
387#define TSEC2_PHY_ADDR 0x1a
388#define TSEC1_PHYIDX 0
389#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500390#define TSEC1_FLAGS TSEC_GIGABIT
391#define TSEC2_FLAGS TSEC_GIGABIT
Paul Gortmaker91e25762007-01-16 11:38:14 -0500392
393/* Options are: TSEC[0-1] */
394#define CONFIG_ETHPRIME "TSEC0"
395
396#endif /* CONFIG_TSEC_ENET */
397
398/*
399 * Environment
400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200402 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200404 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
405 #define CONFIG_ENV_SIZE 0x2000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500406
407/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200408#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
409#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500410
411#else
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500412 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200413 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200415 #define CONFIG_ENV_SIZE 0x2000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500416#endif
417
418#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500420
Jon Loeliger866e3082007-07-04 22:30:58 -0500421
422/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500423 * BOOTP options
424 */
425#define CONFIG_BOOTP_BOOTFILESIZE
426#define CONFIG_BOOTP_BOOTPATH
427#define CONFIG_BOOTP_GATEWAY
428#define CONFIG_BOOTP_HOSTNAME
429
430
431/*
Jon Loeliger866e3082007-07-04 22:30:58 -0500432 * Command line configuration.
433 */
434#include <config_cmd_default.h>
435
436#define CONFIG_CMD_I2C
437#define CONFIG_CMD_MII
438#define CONFIG_CMD_PING
439
Paul Gortmaker91e25762007-01-16 11:38:14 -0500440#if defined(CONFIG_PCI)
Paul Gortmakere4968652007-12-20 12:58:51 -0500441 #define CONFIG_CMD_PCI
Paul Gortmaker91e25762007-01-16 11:38:14 -0500442#endif
443
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500445 #undef CONFIG_CMD_SAVEENV
Jon Loeliger866e3082007-07-04 22:30:58 -0500446 #undef CONFIG_CMD_LOADS
447#endif
448
Paul Gortmaker91e25762007-01-16 11:38:14 -0500449
450#undef CONFIG_WATCHDOG /* watchdog disabled */
451
452/*
453 * Miscellaneous configurable options
454 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_LONGHELP /* undef to save memory */
456#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
457#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500458
Jon Loeliger866e3082007-07-04 22:30:58 -0500459#if defined(CONFIG_CMD_KGDB)
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500460 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500461#else
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500462 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500463#endif
464
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500465 /* Print Buffer Size */
466#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
467#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
468 /* Boot Argument Buffer Size */
469#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
470#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500471
472/*
473 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700474 * have to be in the first 256 MB of memory, since this is
Paul Gortmaker91e25762007-01-16 11:38:14 -0500475 * the maximum mapped by the Linux kernel during initialization.
476 */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500477 /* Initial Memory map for Linux*/
478#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500479
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500481
482#if 1 /*528/264*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500484 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
485 HRCWL_DDR_TO_SCB_CLK_1X1 |\
486 HRCWL_CSB_TO_CLKIN |\
487 HRCWL_VCO_1X2 |\
488 HRCWL_CORE_TO_CSB_2X1)
489#elif 0 /*396/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500491 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
492 HRCWL_DDR_TO_SCB_CLK_1X1 |\
493 HRCWL_CSB_TO_CLKIN |\
494 HRCWL_VCO_1X4 |\
495 HRCWL_CORE_TO_CSB_3X1)
496#elif 0 /*264/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500498 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
499 HRCWL_DDR_TO_SCB_CLK_1X1 |\
500 HRCWL_CSB_TO_CLKIN |\
501 HRCWL_VCO_1X4 |\
502 HRCWL_CORE_TO_CSB_2X1)
503#elif 0 /*132/132*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500505 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
506 HRCWL_DDR_TO_SCB_CLK_1X1 |\
507 HRCWL_CSB_TO_CLKIN |\
508 HRCWL_VCO_1X4 |\
509 HRCWL_CORE_TO_CSB_1X1)
510#elif 0 /*264/264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511#define CONFIG_SYS_HRCW_LOW (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500512 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
513 HRCWL_DDR_TO_SCB_CLK_1X1 |\
514 HRCWL_CSB_TO_CLKIN |\
515 HRCWL_VCO_1X4 |\
516 HRCWL_CORE_TO_CSB_1X1)
517#endif
518
519#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_HRCW_HIGH (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500521 HRCWH_PCI_HOST |\
522 HRCWH_64_BIT_PCI |\
523 HRCWH_PCI1_ARBITER_ENABLE |\
524 HRCWH_PCI2_ARBITER_DISABLE |\
525 HRCWH_CORE_ENABLE |\
526 HRCWH_FROM_0X00000100 |\
527 HRCWH_BOOTSEQ_DISABLE |\
528 HRCWH_SW_WATCHDOG_DISABLE |\
529 HRCWH_ROM_LOC_LOCAL_16BIT |\
530 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500531 HRCWH_TSEC2M_IN_GMII)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500532#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#define CONFIG_SYS_HRCW_HIGH (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500534 HRCWH_PCI_HOST |\
535 HRCWH_32_BIT_PCI |\
536 HRCWH_PCI1_ARBITER_ENABLE |\
537 HRCWH_PCI2_ARBITER_ENABLE |\
538 HRCWH_CORE_ENABLE |\
539 HRCWH_FROM_0X00000100 |\
540 HRCWH_BOOTSEQ_DISABLE |\
541 HRCWH_SW_WATCHDOG_DISABLE |\
542 HRCWH_ROM_LOC_LOCAL_16BIT |\
543 HRCWH_TSEC1M_IN_GMII |\
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500544 HRCWH_TSEC2M_IN_GMII)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500545#endif
546
547/* System IO Config */
Kim Phillips3c9b1ee2009-06-05 14:11:33 -0500548#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200549#define CONFIG_SYS_SICRL SICRL_LDP_A
Paul Gortmaker91e25762007-01-16 11:38:14 -0500550
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200551#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500552#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
553 | HID0_ENABLE_INSTRUCTION_CACHE)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500554
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500555/* #define CONFIG_SYS_HID0_FINAL (\
Paul Gortmaker91e25762007-01-16 11:38:14 -0500556 HID0_ENABLE_INSTRUCTION_CACHE |\
557 HID0_ENABLE_M_BIT |\
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500558 HID0_ENABLE_ADDRESS_BROADCAST) */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500559
560
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561#define CONFIG_SYS_HID2 HID2_HBE
Paul Gortmaker91e25762007-01-16 11:38:14 -0500562
Becky Bruce31d82672008-05-08 19:02:12 -0500563#define CONFIG_HIGH_BATS 1 /* High BATs supported */
564
Paul Gortmaker91e25762007-01-16 11:38:14 -0500565/* DDR @ 0x00000000 */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500566#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500567 | BATL_PP_RW \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500568 | BATL_MEMCOHERENCE)
569#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
570 | BATU_BL_256M \
571 | BATU_VS \
572 | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500573
574/* PCI @ 0x80000000 */
575#ifdef CONFIG_PCI
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500576#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500577 | BATL_PP_RW \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500578 | BATL_MEMCOHERENCE)
579#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
580 | BATU_BL_256M \
581 | BATU_VS \
582 | BATU_VP)
583#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500584 | BATL_PP_RW \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500585 | BATL_CACHEINHIBIT \
586 | BATL_GUARDEDSTORAGE)
587#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
588 | BATU_BL_256M \
589 | BATU_VS \
590 | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500591#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200592#define CONFIG_SYS_IBAT1L (0)
593#define CONFIG_SYS_IBAT1U (0)
594#define CONFIG_SYS_IBAT2L (0)
595#define CONFIG_SYS_IBAT2U (0)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500596#endif
597
598#ifdef CONFIG_MPC83XX_PCI2
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500599#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500600 | BATL_PP_RW \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500601 | BATL_MEMCOHERENCE)
602#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
603 | BATU_BL_256M \
604 | BATU_VS \
605 | BATU_VP)
606#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500607 | BATL_PP_RW \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500608 | BATL_CACHEINHIBIT \
609 | BATL_GUARDEDSTORAGE)
610#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
611 | BATU_BL_256M \
612 | BATU_VS \
613 | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500614#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615#define CONFIG_SYS_IBAT3L (0)
616#define CONFIG_SYS_IBAT3U (0)
617#define CONFIG_SYS_IBAT4L (0)
618#define CONFIG_SYS_IBAT4U (0)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500619#endif
620
621/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500622#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500623 | BATL_PP_RW \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500624 | BATL_CACHEINHIBIT \
625 | BATL_GUARDEDSTORAGE)
626#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
627 | BATU_BL_256M \
628 | BATU_VS \
629 | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500630
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500631/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
632#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500633 | BATL_PP_RW \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500634 | BATL_MEMCOHERENCE \
635 | BATL_GUARDEDSTORAGE)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500636#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \
637 | BATU_BL_256M \
638 | BATU_VS \
639 | BATU_VP)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500640
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200641#define CONFIG_SYS_IBAT7L (0)
642#define CONFIG_SYS_IBAT7U (0)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500643
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200644#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
645#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
646#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
647#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
648#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
649#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
650#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
651#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
652#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
653#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
654#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
655#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
656#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
657#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
658#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
659#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Paul Gortmaker91e25762007-01-16 11:38:14 -0500660
Jon Loeliger866e3082007-07-04 22:30:58 -0500661#if defined(CONFIG_CMD_KGDB)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500662#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
663#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
664#endif
665
666/*
667 * Environment Configuration
668 */
669#define CONFIG_ENV_OVERWRITE
670
671#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500672#define CONFIG_HAS_ETH0
Paul Gortmaker91e25762007-01-16 11:38:14 -0500673#define CONFIG_HAS_ETH1
Paul Gortmaker91e25762007-01-16 11:38:14 -0500674#endif
675
Paul Gortmaker91e25762007-01-16 11:38:14 -0500676#define CONFIG_HOSTNAME SBC8349
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000677#define CONFIG_ROOTPATH "/tftpboot/rootfs"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000678#define CONFIG_BOOTFILE "uImage"
Paul Gortmaker91e25762007-01-16 11:38:14 -0500679
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500680 /* default location for tftp and bootm */
681#define CONFIG_LOADADDR 800000
Paul Gortmaker91e25762007-01-16 11:38:14 -0500682
683#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500684#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500685
686#define CONFIG_BAUDRATE 115200
687
688#define CONFIG_EXTRA_ENV_SETTINGS \
689 "netdev=eth0\0" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200690 "hostname=sbc8349\0" \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500691 "nfsargs=setenv bootargs root=/dev/nfs rw " \
692 "nfsroot=${serverip}:${rootpath}\0" \
693 "ramargs=setenv bootargs root=/dev/ram rw\0" \
694 "addip=setenv bootargs ${bootargs} " \
695 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
696 ":${hostname}:${netdev}:off panic=1\0" \
697 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
698 "flash_nfs=run nfsargs addip addtty;" \
699 "bootm ${kernel_addr}\0" \
700 "flash_self=run ramargs addip addtty;" \
701 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
702 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
703 "bootm\0" \
704 "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \
Paul Gortmakerfe613cd2009-07-23 17:10:55 -0400705 "update=protect off ff800000 ff83ffff; " \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500706 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100707 "upd=run load update\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500708 "fdtaddr=780000\0" \
Detlev Zundela99715b2008-04-18 14:50:01 +0200709 "fdtfile=sbc8349.dtb\0" \
Paul Gortmaker91e25762007-01-16 11:38:14 -0500710 ""
711
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500712#define CONFIG_NFSBOOTCOMMAND \
713 "setenv bootargs root=/dev/nfs rw " \
714 "nfsroot=$serverip:$rootpath " \
715 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
716 "$netdev:off " \
717 "console=$consoledev,$baudrate $othbootargs;" \
718 "tftp $loadaddr $bootfile;" \
719 "tftp $fdtaddr $fdtfile;" \
720 "bootm $loadaddr - $fdtaddr"
Paul Gortmaker91e25762007-01-16 11:38:14 -0500721
722#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger60e1dc12011-10-11 23:57:25 -0500723 "setenv bootargs root=/dev/ram rw " \
724 "console=$consoledev,$baudrate $othbootargs;" \
725 "tftp $ramdiskaddr $ramdiskfile;" \
726 "tftp $loadaddr $bootfile;" \
727 "tftp $fdtaddr $fdtfile;" \
728 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Paul Gortmaker91e25762007-01-16 11:38:14 -0500729
730#define CONFIG_BOOTCOMMAND "run flash_self"
731
732#endif /* __CONFIG_H */