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wdenk48c00102002-10-26 17:39:47 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2002-2005
3 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
wdenk48c00102002-10-26 17:39:47 +00004 * (C) Copyright 2002
5 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 * Gary Jennejohn <gj@denx.de>
8 *
9 * Configuation settings for the SAMSUNG board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenk48c00102002-10-26 17:39:47 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_ARM920T 1 /* This is an ARM920T core */
38#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
39#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
40
41/* input clock of PLL */
wdenk7f6c2cb2002-11-10 22:06:23 +000042#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */
wdenk48c00102002-10-26 17:39:47 +000043#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44
45#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
46#define CONFIG_SETUP_MEMORY_TAGS 1
47#define CONFIG_INITRD_TAG 1
48
49
50/*
51 * Size of malloc() pool
52 */
wdenk699b13a2002-11-03 18:03:52 +000053#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
wdenka8c7c702003-12-06 19:49:23 +000054#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk48c00102002-10-26 17:39:47 +000055
56/*
57 * Hardware drivers
58 */
59#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
60#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */
61#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
62
63/*
64 * select serial console configuration
65 */
66#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SAMSUNG */
67
68#undef CONFIG_HWFLOW /* include RTS/CTS flow control support */
69
70#undef CONFIG_MODEM_SUPPORT /* enable modem initialization stuff */
71
72/*
73 * The following enables modem debugging stuff. The dbg() and
74 * 'char screen[1024]' are used for debug printfs. Unfortunately,
75 * it is usable only from BDI
76 */
77#undef CONFIG_MODEM_SUPPORT_DEBUG
78
79/* allow to overwrite serial and ethaddr */
80#define CONFIG_ENV_OVERWRITE
81
82#define CONFIG_BAUDRATE 115200
83
84#define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */
85
wdenk48b42612003-06-19 23:01:32 +000086/* Use s3c2400's RTC */
87#define CONFIG_RTC_S3C24X0 1
88
Jon Loeliger46da1e92007-07-04 22:33:30 -050089
90/*
Jon Loeliger079a1362007-07-10 10:12:10 -050091 * BOOTP options
92 */
93#define CONFIG_BOOTP_BOOTFILESIZE
94#define CONFIG_BOOTP_BOOTPATH
95#define CONFIG_BOOTP_GATEWAY
96#define CONFIG_BOOTP_HOSTNAME
97
98
99/*
Jon Loeliger46da1e92007-07-04 22:33:30 -0500100 * Command line configuration.
101 */
102#include <config_cmd_default.h>
103
104#define CONFIG_CMD_DATE
105#define CONFIG_CMD_SNTP
106
107#if defined(CONFIG_HWFLOW)
108 #define CONFIG_CONFIG_HWFLOW
wdenk48c00102002-10-26 17:39:47 +0000109#endif
110
Jon Loeliger46da1e92007-07-04 22:33:30 -0500111#if !defined(USE_920T_MMU)
112 #undef CONFIG_CMD_CACHE
wdenk48c00102002-10-26 17:39:47 +0000113#endif
114
wdenk48c00102002-10-26 17:39:47 +0000115
116#define CONFIG_BOOTDELAY 3
117#if 0
118#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
119#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
120#endif
121#define CONFIG_NETMASK 255.255.255.0
122#define CONFIG_IPADDR 134.98.93.36
123#define CONFIG_SERVERIP 134.98.93.22
124#if 0
125#define CONFIG_BOOTFILE "elinos-lart"
126#define CONFIG_BOOTCOMMAND "tftp; bootm"
127#endif
128
Jon Loeliger46da1e92007-07-04 22:33:30 -0500129#if defined(CONFIG_CMD_KGDB)
wdenk48c00102002-10-26 17:39:47 +0000130#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
131/* what's this ? it's not used anywhere */
132#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
133#endif
134
135/*
136 * Miscellaneous configurable options
137 */
138#define CFG_LONGHELP /* undef to save memory */
139#define CFG_PROMPT "SMDK2400 # " /* Monitor Command Prompt */
140#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
141#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
142#define CFG_MAXARGS 16 /* max number of command args */
143#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
144
145#define CFG_MEMTEST_START 0x0c000000 /* memtest works on */
146#define CFG_MEMTEST_END 0x0e000000 /* 32 MB in DRAM */
147
148#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
149
150#define CFG_LOAD_ADDR 0x0cf00000 /* default load address */
151
152/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
153/* it to wrap 100 times (total 1562500) to get 1 sec. */
154#define CFG_HZ 1562500
155
156/* valid baudrates */
157#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
158
159/*-----------------------------------------------------------------------
160 * Stack sizes
161 *
162 * The stack sizes are set up in start.S using the settings below
163 */
164#define CONFIG_STACKSIZE (128*1024) /* regular stack */
165#ifdef CONFIG_USE_IRQ
166#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
167#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
168#endif
169
170/*-----------------------------------------------------------------------
171 * Physical Memory Map
172 */
173#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
174#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
175#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
176
wdenk6069ff22003-02-28 00:49:47 +0000177#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
wdenk48c00102002-10-26 17:39:47 +0000178
179/*-----------------------------------------------------------------------
180 * FLASH and environment organization
181 */
182#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
183#define CFG_MAX_FLASH_SECT (64) /* max number of sectors on one chip */
184
185/* timeout values are in ticks */
186#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
187#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
188
189#define CFG_ENV_IS_IN_FLASH 1
190
191/* Address and size of Primary Environment Sector */
wdenk6069ff22003-02-28 00:49:47 +0000192#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
wdenk48c00102002-10-26 17:39:47 +0000193#define CFG_ENV_SIZE 0x40000
194
195/* Address and size of Redundant Environment Sector */
196#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE)
197#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
198
199#endif /* __CONFIG_H */