blob: afb3e96520b83fcd472757643e4bded2a0f21b14 [file] [log] [blame]
Michal Simek85231c02018-03-28 15:09:32 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZC1232
4 *
Michal Simekd31f1c92020-02-18 08:38:06 +01005 * (C) Copyright 2017 - 2020, Xilinx, Inc.
Michal Simek85231c02018-03-28 15:09:32 +02006 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/phy/phy.h>
15
16/ {
17 model = "ZynqMP ZC1232 RevA";
18 compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &dcc;
23 spi0 = &qspi;
24 };
25
26 chosen {
27 bootargs = "earlycon";
28 stdout-path = "serial0:115200n8";
29 };
30
31 memory@0 {
32 device_type = "memory";
33 reg = <0x0 0x0 0x0 0x80000000>;
34 };
35};
36
37&dcc {
38 status = "okay";
39};
40
41&qspi {
42 status = "okay";
43 flash@0 {
Neil Armstrongffd4c7c2019-02-10 10:16:20 +000044 compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */
Michal Simek85231c02018-03-28 15:09:32 +020045 #address-cells = <1>;
46 #size-cells = <1>;
47 reg = <0x0>;
48 spi-tx-bus-width = <1>;
49 spi-rx-bus-width = <4>;
50 spi-max-frequency = <108000000>; /* Based on DC1 spec */
Michal Simek5df63a62020-02-14 14:19:56 +010051 partition@0 { /* for testing purpose */
Michal Simek85231c02018-03-28 15:09:32 +020052 label = "qspi-fsbl-uboot";
53 reg = <0x0 0x100000>;
54 };
Michal Simek5df63a62020-02-14 14:19:56 +010055 partition@100000 { /* for testing purpose */
Michal Simek85231c02018-03-28 15:09:32 +020056 label = "qspi-linux";
57 reg = <0x100000 0x500000>;
58 };
Michal Simek5df63a62020-02-14 14:19:56 +010059 partition@600000 { /* for testing purpose */
Michal Simek85231c02018-03-28 15:09:32 +020060 label = "qspi-device-tree";
61 reg = <0x600000 0x20000>;
62 };
Michal Simek5df63a62020-02-14 14:19:56 +010063 partition@620000 { /* for testing purpose */
Michal Simek85231c02018-03-28 15:09:32 +020064 label = "qspi-rootfs";
65 reg = <0x620000 0x5E0000>;
66 };
67 };
68};
69
70&sata {
71 status = "okay";
72 /* SATA OOB timing settings */
73 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
74 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
75 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
76 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
77 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
78 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
79 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
80 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
81 phy-names = "sata-phy";
82 phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;
83};
84
85&uart0 {
86 status = "okay";
87};