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Kumar Gala9490a7f2008-07-25 13:31:05 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
Kumar Gala9490a7f2008-07-25 13:31:05 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala9490a7f2008-07-25 13:31:05 -05005 */
6
7/*
8 * mpc8536ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Kumar Galac7e1a432010-05-21 04:14:49 -050014#include "../board/freescale/common/ics307_clk.h"
15
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020016#ifdef CONFIG_36BIT
Kumar Gala337f9fd2009-07-30 15:54:07 -050017#define CONFIG_PHYS_64BIT 1
18#endif
19
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020020#ifdef CONFIG_NAND
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080021#define CONFIG_NAND_U_BOOT 1
22#define CONFIG_RAMBOOT_NAND 1
Haiying Wang96196a12010-11-10 15:37:13 -050023#ifdef CONFIG_NAND_SPL
24#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
25#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
26#else
Kumar Gala00203c62011-01-31 15:57:01 -060027#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0xf8f82000
Haiying Wang96196a12010-11-10 15:37:13 -050029#endif /* CONFIG_NAND_SPL */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +080030#endif
31
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020032#ifdef CONFIG_SDCARD
Mingkai Hue40ac482009-09-23 15:20:38 +080033#define CONFIG_RAMBOOT_SDCARD 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020034#define CONFIG_SYS_TEXT_BASE 0xf8f80000
Kumar Gala7a577fd2011-01-12 02:48:53 -060035#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Mingkai Hue40ac482009-09-23 15:20:38 +080036#endif
37
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020038#ifdef CONFIG_SPIFLASH
Mingkai Hue40ac482009-09-23 15:20:38 +080039#define CONFIG_RAMBOOT_SPIFLASH 1
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xf8f80000
Kumar Gala7a577fd2011-01-12 02:48:53 -060041#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#endif
43
44#ifndef CONFIG_SYS_TEXT_BASE
45#define CONFIG_SYS_TEXT_BASE 0xeff80000
Mingkai Hue40ac482009-09-23 15:20:38 +080046#endif
47
Kumar Gala7a577fd2011-01-12 02:48:53 -060048#ifndef CONFIG_RESET_VECTOR_ADDRESS
49#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
50#endif
51
Haiying Wang96196a12010-11-10 15:37:13 -050052#ifndef CONFIG_SYS_MONITOR_BASE
53#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
54#endif
55
Kumar Gala9490a7f2008-07-25 13:31:05 -050056/* High Level Configuration Options */
57#define CONFIG_BOOKE 1 /* BOOKE */
58#define CONFIG_E500 1 /* BOOKE e500 family */
Kumar Gala9490a7f2008-07-25 13:31:05 -050059#define CONFIG_MPC8536 1
60#define CONFIG_MPC8536DS 1
61
Kumar Galac51fc5d2009-01-23 14:22:13 -060062#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
Xie Xiaoboae2044d2011-10-03 12:18:39 -070063#define CONFIG_SPI_FLASH 1 /* Has SPI Flash */
Kumar Gala9490a7f2008-07-25 13:31:05 -050064#define CONFIG_PCI 1 /* Enable PCI/PCIE */
65#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
66#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
67#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
68#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
69#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000070#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala9490a7f2008-07-25 13:31:05 -050071#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala0151cba2008-10-21 11:33:58 -050072#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Kumar Gala9490a7f2008-07-25 13:31:05 -050073
74#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Roy Zangf6155c62009-07-09 10:05:48 +080075#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/
Kumar Gala9490a7f2008-07-25 13:31:05 -050076
77#define CONFIG_TSEC_ENET /* tsec ethernet support */
78#define CONFIG_ENV_OVERWRITE
79
Kumar Galac7e1a432010-05-21 04:14:49 -050080#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
81#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
Kumar Gala9490a7f2008-07-25 13:31:05 -050082#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
Kumar Gala9490a7f2008-07-25 13:31:05 -050083
84/*
85 * These can be toggled for performance analysis, otherwise use default.
86 */
87#define CONFIG_L2_CACHE /* toggle L2 cache */
88#define CONFIG_BTB /* toggle branch predition */
Kumar Gala9490a7f2008-07-25 13:31:05 -050089
Andy Fleming80522dc2008-10-30 16:51:33 -050090#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
91
Kumar Gala9490a7f2008-07-25 13:31:05 -050092#define CONFIG_ENABLE_36BIT_PHYS 1
93
Kumar Gala337f9fd2009-07-30 15:54:07 -050094#ifdef CONFIG_PHYS_64BIT
95#define CONFIG_ADDR_MAP 1
96#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
97#endif
98
Mingkai Hu07355702009-09-23 15:19:32 +080099#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
100#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500101#define CONFIG_PANIC_HANG /* do not reset board on panic */
102
103/*
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800104 * Config the L2 Cache as L2 SRAM
105 */
106#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
107#ifdef CONFIG_PHYS_64BIT
108#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
109#else
110#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
111#endif
112#define CONFIG_SYS_L2_SIZE (512 << 10)
113#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
114
Timur Tabie46fedf2011-08-04 18:03:41 -0500115#define CONFIG_SYS_CCSRBAR 0xffe00000
116#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Kumar Gala9490a7f2008-07-25 13:31:05 -0500117
Kumar Gala8d22ddc2011-11-09 09:10:49 -0600118#if defined(CONFIG_NAND_SPL)
Timur Tabie46fedf2011-08-04 18:03:41 -0500119#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800120#endif
121
Kumar Gala9490a7f2008-07-25 13:31:05 -0500122/* DDR Setup */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500123#define CONFIG_VERY_BIG_RAM
York Sun5614e712013-09-30 09:22:09 -0700124#define CONFIG_SYS_FSL_DDR2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500125#undef CONFIG_FSL_DDR_INTERACTIVE
126#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
127#define CONFIG_DDR_SPD
Kumar Gala9490a7f2008-07-25 13:31:05 -0500128
Dave Liu9b0ad1b2008-10-28 17:53:38 +0800129#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500130#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
133#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala9490a7f2008-07-25 13:31:05 -0500134
135#define CONFIG_NUM_DDR_CONTROLLERS 1
136#define CONFIG_DIMM_SLOTS_PER_CTLR 1
137#define CONFIG_CHIP_SELECTS_PER_CTRL 2
138
139/* I2C addresses of SPD EEPROMs */
140#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500142
143/* These are used when DDR doesn't use SPD. */
Mingkai Hu07355702009-09-23 15:19:32 +0800144#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
Mingkai Hu07355702009-09-23 15:19:32 +0800146#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_DDR_TIMING_3 0x00000000
148#define CONFIG_SYS_DDR_TIMING_0 0x00260802
149#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
150#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
151#define CONFIG_SYS_DDR_MODE_1 0x00480432
152#define CONFIG_SYS_DDR_MODE_2 0x00000000
153#define CONFIG_SYS_DDR_INTERVAL 0x06180100
154#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
155#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
156#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
157#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
Mingkai Hu07355702009-09-23 15:19:32 +0800158#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_DDR_CONTROL2 0x04400010
Kumar Gala9490a7f2008-07-25 13:31:05 -0500160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
162#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
163#define CONFIG_SYS_DDR_SBE 0x00010000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500164
Kumar Gala9490a7f2008-07-25 13:31:05 -0500165/* Make sure required options are set */
166#ifndef CONFIG_SPD_EEPROM
167#error ("CONFIG_SPD_EEPROM is required")
168#endif
169
170#undef CONFIG_CLOCKS_IN_MHZ
171
172
173/*
174 * Memory map -- xxx -this is wrong, needs updating
175 *
176 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
177 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
178 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
179 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
180 *
181 * Localbus cacheable (TBD)
182 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
183 *
184 * Localbus non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500185 * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500186 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Jason Jinc57fc282008-10-31 05:07:04 -0500187 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
Kumar Gala9490a7f2008-07-25 13:31:05 -0500188 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
189 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
190 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
191 */
192
193/*
194 * Local Bus Definitions
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500197#ifdef CONFIG_PHYS_64BIT
198#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
199#else
Kumar Galac953ddf2008-12-02 14:19:34 -0600200#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500201#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500202
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800203#define CONFIG_FLASH_BR_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000204 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800205#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500206
Mingkai Hu07355702009-09-23 15:19:32 +0800207#define CONFIG_SYS_BR1_PRELIM \
208 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
209 | BR_PS_16 | BR_V)
Kumar Galac953ddf2008-12-02 14:19:34 -0600210#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500211
Mingkai Hu07355702009-09-23 15:19:32 +0800212#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
213 CONFIG_SYS_FLASH_BASE_PHYS }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_FLASH_QUIET_TEST
Kumar Gala9490a7f2008-07-25 13:31:05 -0500215#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
216
Mingkai Hu07355702009-09-23 15:19:32 +0800217#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
218#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#undef CONFIG_SYS_FLASH_CHECKSUM
Mingkai Hu07355702009-09-23 15:19:32 +0800220#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
221#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500222
Kumar Galaa55bb832010-11-29 14:32:11 -0600223#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
224 defined(CONFIG_RAMBOOT_SPIFLASH)
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800225#define CONFIG_SYS_RAMBOOT
Kumar Galaa55bb832010-11-29 14:32:11 -0600226#define CONFIG_SYS_EXTRA_ENV_RELOC
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800227#else
228#undef CONFIG_SYS_RAMBOOT
229#endif
230
Kumar Gala9490a7f2008-07-25 13:31:05 -0500231#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_FLASH_CFI
233#define CONFIG_SYS_FLASH_EMPTY_INFO
234#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
Kumar Gala9490a7f2008-07-25 13:31:05 -0500235
236#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
237
Ramneek Mehresh68d42302011-06-07 10:10:43 +0000238#define CONFIG_HWCONFIG /* enable hwconfig */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500239#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
240#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500241#ifdef CONFIG_PHYS_64BIT
242#define PIXIS_BASE_PHYS 0xfffdf0000ull
243#else
Kumar Gala52b565f2008-12-02 14:19:33 -0600244#define PIXIS_BASE_PHYS PIXIS_BASE
Kumar Gala337f9fd2009-07-30 15:54:07 -0500245#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500246
Kumar Gala52b565f2008-12-02 14:19:33 -0600247#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
Mingkai Hu07355702009-09-23 15:19:32 +0800248#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500249
250#define PIXIS_ID 0x0 /* Board ID at offset 0 */
251#define PIXIS_VER 0x1 /* Board version at offset 1 */
252#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
253#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
254#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
255#define PIXIS_PWR 0x5 /* PIXIS Power status register */
256#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
257#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
258#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
259#define PIXIS_VCTL 0x10 /* VELA Control Register */
260#define PIXIS_VSTAT 0x11 /* VELA Status Register */
261#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
262#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
263#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
264#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala6bb5b412009-07-14 22:42:01 -0500265#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
266#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
267#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
268#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
269#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
270#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
271#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500272#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
273#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
274#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
275#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
276#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
277#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
278#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
279#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
280#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
281#define PIXIS_VWATCH 0x24 /* Watchdog Register */
282#define PIXIS_LED 0x25 /* LED Register */
283
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800284#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
285
Kumar Gala9490a7f2008-07-25 13:31:05 -0500286/* old pixis referenced names */
287#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
288#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Matthew McClintock509e19c2011-02-25 16:20:11 -0600289#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
Kumar Gala9490a7f2008-07-25 13:31:05 -0500290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_INIT_RAM_LOCK 1
292#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200293#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500294
Mingkai Hu07355702009-09-23 15:19:32 +0800295#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200296 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Kumar Gala9490a7f2008-07-25 13:31:05 -0500298
Mingkai Hu07355702009-09-23 15:19:32 +0800299#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
300#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500301
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800302#ifndef CONFIG_NAND_SPL
Kumar Gala337f9fd2009-07-30 15:54:07 -0500303#define CONFIG_SYS_NAND_BASE 0xffa00000
304#ifdef CONFIG_PHYS_64BIT
305#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
306#else
307#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
308#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800309#else
310#define CONFIG_SYS_NAND_BASE 0xfff00000
311#ifdef CONFIG_PHYS_64BIT
312#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
313#else
314#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
315#endif
316#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500317#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
318 CONFIG_SYS_NAND_BASE + 0x40000, \
319 CONFIG_SYS_NAND_BASE + 0x80000, \
320 CONFIG_SYS_NAND_BASE + 0xC0000}
321#define CONFIG_SYS_MAX_NAND_DEVICE 4
Jason Jinc57fc282008-10-31 05:07:04 -0500322#define CONFIG_MTD_NAND_VERIFY_WRITE
323#define CONFIG_CMD_NAND 1
324#define CONFIG_NAND_FSL_ELBC 1
325#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
326
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800327/* NAND boot: 4K NAND loader config */
328#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
329#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
330#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
331#define CONFIG_SYS_NAND_U_BOOT_START \
332 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
333#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
334#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
335#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
336
Jason Jinc57fc282008-10-31 05:07:04 -0500337/* NAND flash config */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500338#define CONFIG_SYS_NAND_BR_PRELIM \
Mingkai Hu07355702009-09-23 15:19:32 +0800339 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
340 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
341 | BR_PS_8 /* Port Size = 8 bit */ \
342 | BR_MS_FCM /* MSEL = FCM */ \
343 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500344#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
Mingkai Hu07355702009-09-23 15:19:32 +0800345 | OR_FCM_PGS /* Large Page*/ \
346 | OR_FCM_CSCT \
347 | OR_FCM_CST \
348 | OR_FCM_CHT \
349 | OR_FCM_SCY_1 \
350 | OR_FCM_TRLX \
351 | OR_FCM_EHTR)
Jason Jinc57fc282008-10-31 05:07:04 -0500352
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800353#ifdef CONFIG_RAMBOOT_NAND
Matthew McClintocka3055c52011-04-05 14:39:33 -0500354#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
355#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800356#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
357#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
358#else
359#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
360#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500361#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
362#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800363#endif
Jason Jinc57fc282008-10-31 05:07:04 -0500364
Mingkai Hu07355702009-09-23 15:19:32 +0800365#define CONFIG_SYS_BR4_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000366 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800367 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
368 | BR_PS_8 /* Port Size = 8 bit */ \
369 | BR_MS_FCM /* MSEL = FCM */ \
370 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500371#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Mingkai Hu07355702009-09-23 15:19:32 +0800372#define CONFIG_SYS_BR5_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000373 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800374 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
375 | BR_PS_8 /* Port Size = 8 bit */ \
376 | BR_MS_FCM /* MSEL = FCM */ \
377 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500378#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500379
Mingkai Hu07355702009-09-23 15:19:32 +0800380#define CONFIG_SYS_BR6_PRELIM \
Timur Tabi7ee41102012-07-06 07:39:26 +0000381 (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
Mingkai Hu07355702009-09-23 15:19:32 +0800382 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
383 | BR_PS_8 /* Port Size = 8 bit */ \
384 | BR_MS_FCM /* MSEL = FCM */ \
385 | BR_V) /* valid */
Matthew McClintocka3055c52011-04-05 14:39:33 -0500386#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
Jason Jinc57fc282008-10-31 05:07:04 -0500387
Kumar Gala9490a7f2008-07-25 13:31:05 -0500388/* Serial Port - controlled on board with jumper J8
389 * open - index 2
390 * shorted - index 1
391 */
392#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_NS16550
394#define CONFIG_SYS_NS16550_SERIAL
395#define CONFIG_SYS_NS16550_REG_SIZE 1
396#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kumar Gala93341902010-04-07 01:34:11 -0500397#ifdef CONFIG_NAND_SPL
398#define CONFIG_NS16550_MIN_FUNCTIONS
399#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500400
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_BAUDRATE_TABLE \
Kumar Gala9490a7f2008-07-25 13:31:05 -0500402 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
403
Mingkai Hu07355702009-09-23 15:19:32 +0800404#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
405#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
Kumar Gala9490a7f2008-07-25 13:31:05 -0500406
407/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_HUSH_PARSER
Kumar Gala9490a7f2008-07-25 13:31:05 -0500409
410/*
411 * Pass open firmware flat tree
412 */
413#define CONFIG_OF_LIBFDT 1
414#define CONFIG_OF_BOARD_SETUP 1
415#define CONFIG_OF_STDOUT_VIA_ALIAS 1
416
Kumar Gala9490a7f2008-07-25 13:31:05 -0500417/*
418 * I2C
419 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200420#define CONFIG_SYS_I2C
421#define CONFIG_SYS_I2C_FSL
422#define CONFIG_SYS_FSL_I2C_SPEED 400000
423#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
424#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
425#define CONFIG_SYS_FSL_I2C2_SPEED 400000
426#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
427#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
428#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
Kumar Gala9490a7f2008-07-25 13:31:05 -0500429
430/*
431 * I2C2 EEPROM
432 */
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200433#define CONFIG_ID_EEPROM
434#ifdef CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_I2C_EEPROM_NXID
Kumar Gala9490a7f2008-07-25 13:31:05 -0500436#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
438#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
439#define CONFIG_SYS_EEPROM_BUS_NUM 1
Kumar Gala9490a7f2008-07-25 13:31:05 -0500440
441/*
Xie Xiaoboae2044d2011-10-03 12:18:39 -0700442 * eSPI - Enhanced SPI
443 */
444#define CONFIG_HARD_SPI
445#define CONFIG_FSL_ESPI
446
447#if defined(CONFIG_SPI_FLASH)
448#define CONFIG_SPI_FLASH_SPANSION
449#define CONFIG_CMD_SF
450#define CONFIG_SF_DEFAULT_SPEED 10000000
451#define CONFIG_SF_DEFAULT_MODE 0
452#endif
453
454/*
Kumar Gala9490a7f2008-07-25 13:31:05 -0500455 * General PCI
456 * Memory space is mapped 1-1, but I/O space must start from 0.
457 */
458
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600459#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500460#ifdef CONFIG_PHYS_64BIT
461#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
462#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
463#else
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600464#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
465#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500466#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala337f9fd2009-07-30 15:54:07 -0500468#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
469#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
470#ifdef CONFIG_PHYS_64BIT
471#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
472#else
473#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
474#endif
475#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500476
477/* controller 1, Slot 1, tgtid 1, Base address a000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600478#define CONFIG_SYS_PCIE1_NAME "Slot 1"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600479#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500480#ifdef CONFIG_PHYS_64BIT
481#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
482#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
483#else
Kumar Gala10795f42008-12-02 16:08:36 -0600484#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600485#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500486#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600488#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500489#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
490#ifdef CONFIG_PHYS_64BIT
491#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
492#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500494#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200495#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500496
497/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600498#define CONFIG_SYS_PCIE2_NAME "Slot 2"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600499#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500500#ifdef CONFIG_PHYS_64BIT
501#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
502#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
503#else
Kumar Gala10795f42008-12-02 16:08:36 -0600504#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600505#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500506#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600508#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500509#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
510#ifdef CONFIG_PHYS_64BIT
511#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
512#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500514#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500516
517/* controller 3, direct to uli, tgtid 3, Base address 8000 */
Kumar Gala5f7b31b2010-12-17 15:14:54 -0600518#define CONFIG_SYS_PCIE3_NAME "Slot 3"
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600519#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500520#ifdef CONFIG_PHYS_64BIT
521#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
522#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
523#else
Kumar Gala10795f42008-12-02 16:08:36 -0600524#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600525#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500526#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600528#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500529#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
530#ifdef CONFIG_PHYS_64BIT
531#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
532#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
Kumar Gala337f9fd2009-07-30 15:54:07 -0500534#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500536
537#if defined(CONFIG_PCI)
538
Kumar Gala9490a7f2008-07-25 13:31:05 -0500539#define CONFIG_PCI_PNP /* do pci plug-and-play */
540
541/*PCIE video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600542#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500543
544/*PCI video card used*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600545/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala9490a7f2008-07-25 13:31:05 -0500546
547/* video */
548#define CONFIG_VIDEO
549
550#if defined(CONFIG_VIDEO)
551#define CONFIG_BIOSEMU
552#define CONFIG_CFB_CONSOLE
553#define CONFIG_VIDEO_SW_CURSOR
554#define CONFIG_VGA_AS_SINGLE_DEVICE
555#define CONFIG_ATI_RADEON_FB
556#define CONFIG_VIDEO_LOGO
557/*#define CONFIG_CONSOLE_CURSOR*/
Kumar Galaaca5f012008-12-02 16:08:40 -0600558#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
Kumar Gala9490a7f2008-07-25 13:31:05 -0500559#endif
560
561#undef CONFIG_EEPRO100
562#undef CONFIG_TULIP
563#undef CONFIG_RTL8139
564
Kumar Gala9490a7f2008-07-25 13:31:05 -0500565#ifndef CONFIG_PCI_PNP
Kumar Gala5f91ef62008-12-02 16:08:37 -0600566 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
567 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Kumar Gala9490a7f2008-07-25 13:31:05 -0500568 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
569#endif
570
571#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
572
573#endif /* CONFIG_PCI */
574
575/* SATA */
576#define CONFIG_LIBATA
577#define CONFIG_FSL_SATA
578
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kumar Gala9490a7f2008-07-25 13:31:05 -0500580#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
582#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500583#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200584#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
585#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kumar Gala9490a7f2008-07-25 13:31:05 -0500586
587#ifdef CONFIG_FSL_SATA
588#define CONFIG_LBA48
589#define CONFIG_CMD_SATA
590#define CONFIG_DOS_PARTITION
591#define CONFIG_CMD_EXT2
592#endif
593
594#if defined(CONFIG_TSEC_ENET)
595
Kumar Gala9490a7f2008-07-25 13:31:05 -0500596#define CONFIG_MII 1 /* MII PHY management */
597#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
598#define CONFIG_TSEC1 1
599#define CONFIG_TSEC1_NAME "eTSEC1"
600#define CONFIG_TSEC3 1
601#define CONFIG_TSEC3_NAME "eTSEC3"
602
Jason Jin2e26d832008-10-10 11:41:00 +0800603#define CONFIG_FSL_SGMII_RISER 1
604#define SGMII_RISER_PHY_OFFSET 0x1c
605
Kumar Gala9490a7f2008-07-25 13:31:05 -0500606#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
607#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
608
609#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
610#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
611
612#define TSEC1_PHYIDX 0
613#define TSEC3_PHYIDX 0
614
615#define CONFIG_ETHPRIME "eTSEC1"
616
617#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
618
619#endif /* CONFIG_TSEC_ENET */
620
621/*
622 * Environment
623 */
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800624
625#if defined(CONFIG_SYS_RAMBOOT)
626#if defined(CONFIG_RAMBOOT_NAND)
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700627#define CONFIG_ENV_IS_IN_NAND 1
628#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
629#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
630#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
631#elif defined(CONFIG_RAMBOOT_SPIFLASH)
632#define CONFIG_ENV_IS_IN_SPI_FLASH
633#define CONFIG_ENV_SPI_BUS 0
634#define CONFIG_ENV_SPI_CS 0
635#define CONFIG_ENV_SPI_MAX_HZ 10000000
636#define CONFIG_ENV_SPI_MODE 0
637#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
638#define CONFIG_ENV_OFFSET 0xF0000
639#define CONFIG_ENV_SECT_SIZE 0x10000
640#elif defined(CONFIG_RAMBOOT_SDCARD)
641#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000642#define CONFIG_FSL_FIXED_MMC_LOCATION
Xie Xiaobo2d4afd42011-10-03 12:54:21 -0700643#define CONFIG_ENV_SIZE 0x2000
644#define CONFIG_SYS_MMC_ENV_DEV 0
645#else
Mingkai Hue40ac482009-09-23 15:20:38 +0800646 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
647 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
648 #define CONFIG_ENV_SIZE 0x2000
Kumar Gala9490a7f2008-07-25 13:31:05 -0500649#endif
Mingkai Hu9a1a0ae2009-09-23 15:20:37 +0800650#else
651 #define CONFIG_ENV_IS_IN_FLASH 1
652 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
653 #define CONFIG_ENV_ADDR 0xfff80000
654 #else
655 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
656 #endif
657 #define CONFIG_ENV_SIZE 0x2000
658 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
659#endif
Kumar Gala9490a7f2008-07-25 13:31:05 -0500660
661#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200662#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500663
664/*
665 * Command line configuration.
666 */
667#include <config_cmd_default.h>
668
669#define CONFIG_CMD_IRQ
670#define CONFIG_CMD_PING
671#define CONFIG_CMD_I2C
672#define CONFIG_CMD_MII
673#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500674#define CONFIG_CMD_IRQ
675#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500676#define CONFIG_CMD_REGINFO
Kumar Gala9490a7f2008-07-25 13:31:05 -0500677
678#if defined(CONFIG_PCI)
679#define CONFIG_CMD_PCI
Kumar Gala9490a7f2008-07-25 13:31:05 -0500680#define CONFIG_CMD_NET
681#endif
682
683#undef CONFIG_WATCHDOG /* watchdog disabled */
684
Andy Fleming80522dc2008-10-30 16:51:33 -0500685#define CONFIG_MMC 1
686
687#ifdef CONFIG_MMC
688#define CONFIG_FSL_ESDHC
689#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
690#define CONFIG_CMD_MMC
691#define CONFIG_GENERIC_MMC
Fanzc1116ebb2011-10-03 12:18:42 -0700692#endif
693
694/*
695 * USB
696 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000697#define CONFIG_HAS_FSL_MPH_USB
698#ifdef CONFIG_HAS_FSL_MPH_USB
Fanzc1116ebb2011-10-03 12:18:42 -0700699#define CONFIG_USB_EHCI
700
701#ifdef CONFIG_USB_EHCI
702#define CONFIG_CMD_USB
703#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
704#define CONFIG_USB_EHCI_FSL
705#define CONFIG_USB_STORAGE
706#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000707#endif
Fanzc1116ebb2011-10-03 12:18:42 -0700708
709#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
Andy Fleming80522dc2008-10-30 16:51:33 -0500710#define CONFIG_CMD_EXT2
711#define CONFIG_CMD_FAT
712#define CONFIG_DOS_PARTITION
713#endif
714
Kumar Gala9490a7f2008-07-25 13:31:05 -0500715/*
716 * Miscellaneous configurable options
717 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200718#define CONFIG_SYS_LONGHELP /* undef to save memory */
Mingkai Hu07355702009-09-23 15:19:32 +0800719#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500720#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200721#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500722#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200723#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500724#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200725#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500726#endif
Mingkai Hu07355702009-09-23 15:19:32 +0800727#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
728 + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200729#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
Mingkai Hu07355702009-09-23 15:19:32 +0800730#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500731
732/*
733 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500734 * have to be in the first 64 MB of memory, since this is
Kumar Gala9490a7f2008-07-25 13:31:05 -0500735 * the maximum mapped by the Linux kernel during initialization.
736 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500737#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
738#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500739
Kumar Gala9490a7f2008-07-25 13:31:05 -0500740#if defined(CONFIG_CMD_KGDB)
741#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500742#endif
743
744/*
745 * Environment Configuration
746 */
747
748/* The mac addresses for all ethernet interface */
749#if defined(CONFIG_TSEC_ENET)
750#define CONFIG_HAS_ETH0
751#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
752#define CONFIG_HAS_ETH1
753#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
754#define CONFIG_HAS_ETH2
755#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
756#define CONFIG_HAS_ETH3
757#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
758#endif
759
760#define CONFIG_IPADDR 192.168.1.254
761
762#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000763#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000764#define CONFIG_BOOTFILE "uImage"
Mingkai Hu07355702009-09-23 15:19:32 +0800765#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Kumar Gala9490a7f2008-07-25 13:31:05 -0500766
767#define CONFIG_SERVERIP 192.168.1.1
768#define CONFIG_GATEWAYIP 192.168.1.1
769#define CONFIG_NETMASK 255.255.255.0
770
771/* default location for tftp and bootm */
772#define CONFIG_LOADADDR 1000000
773
774#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
775#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
776
777#define CONFIG_BAUDRATE 115200
778
779#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200780"netdev=eth0\0" \
781"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
782"tftpflash=tftpboot $loadaddr $uboot; " \
783 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
784 " +$filesize; " \
785 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
786 " +$filesize; " \
787 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
788 " $filesize; " \
789 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
790 " +$filesize; " \
791 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
792 " $filesize\0" \
793"consoledev=ttyS0\0" \
794"ramdiskaddr=2000000\0" \
795"ramdiskfile=8536ds/ramdisk.uboot\0" \
796"fdtaddr=c00000\0" \
797"fdtfile=8536ds/mpc8536ds.dtb\0" \
798"bdev=sda3\0" \
799"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
Kumar Gala9490a7f2008-07-25 13:31:05 -0500800
801#define CONFIG_HDBOOT \
802 "setenv bootargs root=/dev/$bdev rw " \
803 "console=$consoledev,$baudrate $othbootargs;" \
804 "tftp $loadaddr $bootfile;" \
805 "tftp $fdtaddr $fdtfile;" \
806 "bootm $loadaddr - $fdtaddr"
807
808#define CONFIG_NFSBOOTCOMMAND \
809 "setenv bootargs root=/dev/nfs rw " \
810 "nfsroot=$serverip:$rootpath " \
811 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
812 "console=$consoledev,$baudrate $othbootargs;" \
813 "tftp $loadaddr $bootfile;" \
814 "tftp $fdtaddr $fdtfile;" \
815 "bootm $loadaddr - $fdtaddr"
816
817#define CONFIG_RAMBOOTCOMMAND \
818 "setenv bootargs root=/dev/ram rw " \
819 "console=$consoledev,$baudrate $othbootargs;" \
820 "tftp $ramdiskaddr $ramdiskfile;" \
821 "tftp $loadaddr $bootfile;" \
822 "tftp $fdtaddr $fdtfile;" \
823 "bootm $loadaddr $ramdiskaddr $fdtaddr"
824
825#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
826
827#endif /* __CONFIG_H */