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TsiChungLiewa1436a82007-08-16 13:20:50 -05001/*
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiewa1436a82007-08-16 13:20:50 -05006 */
7
8#ifndef _M5253EVBE_H
9#define _M5253EVBE_H
10
TsiChungLiewa1436a82007-08-16 13:20:50 -050011#define CONFIG_M5253EVBE /* define board type */
12
13#define CONFIG_MCFTMR
14
15#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020016#define CONFIG_SYS_UART_PORT (0)
TsiChungLiewa1436a82007-08-16 13:20:50 -050017
18#undef CONFIG_WATCHDOG /* disable watchdog */
19
TsiChungLiewa1436a82007-08-16 13:20:50 -050020
21/* Configuration for environment
22 * Environment is embedded in u-boot in the second sector of the flash
23 */
24#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020025#define CONFIG_ENV_OFFSET 0x4000
26#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020027#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiewa1436a82007-08-16 13:20:50 -050028#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020029#define CONFIG_ENV_ADDR 0xffe04000
30#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020031#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiewa1436a82007-08-16 13:20:50 -050032#endif
33
angelo@sysam.it5296cb12015-03-29 22:54:16 +020034#define LDS_BOARD_TEXT \
35 . = DEFINED(env_offset) ? env_offset : .; \
36 common/env_embedded.o (.text)
37
TsiChungLiewa1436a82007-08-16 13:20:50 -050038/*
39 * BOOTP options
40 */
41#undef CONFIG_BOOTP_BOOTFILESIZE
42#undef CONFIG_BOOTP_BOOTPATH
43#undef CONFIG_BOOTP_GATEWAY
44#undef CONFIG_BOOTP_HOSTNAME
45
46/*
47 * Command line configuration.
48 */
TsiChungLiewa1436a82007-08-16 13:20:50 -050049#define CONFIG_CMD_IDE
TsiChungLiewa1436a82007-08-16 13:20:50 -050050
51/* ATA */
TsiChungLiewa1436a82007-08-16 13:20:50 -050052#define CONFIG_IDE_RESET 1
53#define CONFIG_IDE_PREINIT 1
54#define CONFIG_ATAPI
55#undef CONFIG_LBA48
56
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_IDE_MAXBUS 1
58#define CONFIG_SYS_IDE_MAXDEVICE 2
TsiChungLiewa1436a82007-08-16 13:20:50 -050059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
61#define CONFIG_SYS_ATA_IDE0_OFFSET 0
TsiChungLiewa1436a82007-08-16 13:20:50 -050062
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
64#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
65#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
66#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
TsiChungLiewa1436a82007-08-16 13:20:50 -050067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiewa1436a82007-08-16 13:20:50 -050069
70#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiewa1436a82007-08-16 13:20:50 -050072#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiewa1436a82007-08-16 13:20:50 -050074#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
76#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
77#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChungLiewa1436a82007-08-16 13:20:50 -050078
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_LOAD_ADDR 0x00100000
TsiChungLiewa1436a82007-08-16 13:20:50 -050080
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_MEMTEST_START 0x400
82#define CONFIG_SYS_MEMTEST_END 0x380000
TsiChungLiewa1436a82007-08-16 13:20:50 -050083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
85#define CONFIG_SYS_FAST_CLK
86#ifdef CONFIG_SYS_FAST_CLK
87# define CONFIG_SYS_PLLCR 0x1243E054
88# define CONFIG_SYS_CLK 140000000
TsiChungLiewa1436a82007-08-16 13:20:50 -050089#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090# define CONFIG_SYS_PLLCR 0x135a4140
91# define CONFIG_SYS_CLK 70000000
TsiChungLiewa1436a82007-08-16 13:20:50 -050092#endif
93
94/*
95 * Low Level Configuration Settings
96 * (address mappings, register initial values, etc.)
97 * You should know what you are doing if you make changes here.
98 */
99
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
101#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
TsiChungLiewa1436a82007-08-16 13:20:50 -0500102
103/*
104 * Definitions for initial stack pointer and data area (in DPRAM)
105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200107#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200108#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiewa1436a82007-08-16 13:20:50 -0500110
111/*
112 * Start addresses for the final memory configuration
113 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiewa1436a82007-08-16 13:20:50 -0500115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_SDRAM_BASE 0x00000000
117#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
TsiChungLiewa1436a82007-08-16 13:20:50 -0500118
119#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MONITOR_BASE 0x20000
TsiChungLiewa1436a82007-08-16 13:20:50 -0500121#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChungLiewa1436a82007-08-16 13:20:50 -0500123#endif
124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_MONITOR_LEN 0x40000
126#define CONFIG_SYS_MALLOC_LEN (256 << 10)
127#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
TsiChungLiewa1436a82007-08-16 13:20:50 -0500128
129/*
130 * For booting Linux, the board info and command line data
131 * have to be in the first 8 MB of memory, since this is
132 * the maximum mapped by the Linux kernel during initialization ??
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000135#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiewa1436a82007-08-16 13:20:50 -0500136
137/* FLASH organization */
TsiChung Liew012522f2008-10-21 10:03:07 +0000138#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
140#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
141#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
TsiChungLiewa1436a82007-08-16 13:20:50 -0500142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200144#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_FLASH_SIZE 0x200000
146#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
TsiChungLiewa1436a82007-08-16 13:20:50 -0500147
148/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiewa1436a82007-08-16 13:20:50 -0500150
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600151#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200152 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600153#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200154 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600155#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
156#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
157 CF_ADDRMASK(2) | \
158 CF_ACR_EN | CF_ACR_SM_ALL)
159#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
160 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
161 CF_ACR_EN | CF_ACR_SM_ALL)
162#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
163 CF_CACR_DBWE)
164
TsiChungLiewa1436a82007-08-16 13:20:50 -0500165/* Port configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_FECI2C 0xF0
TsiChungLiewa1436a82007-08-16 13:20:50 -0500167
TsiChung Liew012522f2008-10-21 10:03:07 +0000168#define CONFIG_SYS_CS0_BASE 0xFFE00000
169#define CONFIG_SYS_CS0_MASK 0x001F0021
170#define CONFIG_SYS_CS0_CTRL 0x00001D80
TsiChungLiewa1436a82007-08-16 13:20:50 -0500171
172/*-----------------------------------------------------------------------
173 * Port configuration
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
176#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
177#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
178#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
179#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
180#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
181#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
TsiChungLiewa1436a82007-08-16 13:20:50 -0500182
183#endif /* _M5253EVB_H */