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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 09e89ab4af01c551246b3d08f8b31a24ee035ae8 / . / arch / arm / mach-uniphier / sc-regs.h
blob: a0955893ef774cc215eff2c92b45862776091f7f [file] [log] [blame]
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]1/*
2 * UniPhier SC (System Control) block registers
3 *
Masahiro Yamada3365b4e2015-07-21 14:04:22 +0900[diff] [blame]4 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef ARCH_SC_REGS_H
10#define ARCH_SC_REGS_H
11
Masahiro Yamadaea65c982016-03-18 16:41:43 +0900[diff] [blame]12#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
Masahiro Yamada3365b4e2015-07-21 14:04:22 +0900[diff] [blame]13#define SC_BASE_ADDR 0xf1840000
14#else
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]15#define SC_BASE_ADDR 0x61840000
Masahiro Yamada3365b4e2015-07-21 14:04:22 +0900[diff] [blame]16#endif
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]17
Masahiro Yamada28f40d42015-09-22 00:27:40 +0900[diff] [blame]18#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
19#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
20#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
21
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]22#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
23#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
24#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
25#define SC_DPLLCTRL_SSC_RATE (0x1 << 15)
26
27#define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204)
28#define SC_DPLLCTRL2_NRSTDS (0x1 << 28)
29
30#define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208)
31#define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31)
32#define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31)
33
34#define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210)
35
36#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270)
37#define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274)
38#define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278)
39
40#define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290)
41#define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294)
42#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
43
44#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
Masahiro Yamada15351632015-02-27 02:26:58 +0900[diff] [blame]45#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
46#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]47#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
Masahiro Yamada42ca6982015-02-27 02:26:53 +0900[diff] [blame]48#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
Masahiro Yamada15351632015-02-27 02:26:58 +0900[diff] [blame]49#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
Masahiro Yamada28f40d42015-09-22 00:27:40 +0900[diff] [blame]50/* Pro4 or older */
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]51#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
52#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
53#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
54
55#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
Masahiro Yamada15351632015-02-27 02:26:58 +0900[diff] [blame]56#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
57#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
58
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]59#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
60
Masahiro Yamada28f40d42015-09-22 00:27:40 +0900[diff] [blame]61/* Pro5 or newer */
62#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
63#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
64#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
65#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
66#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
Masahiro Yamada019df872015-09-22 00:27:41 +0900[diff] [blame]67#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
Masahiro Yamada28f40d42015-09-22 00:27:40 +0900[diff] [blame]68#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
69#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
70
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]71#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
Masahiro Yamada15351632015-02-27 02:26:58 +0900[diff] [blame]72#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
73#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
Masahiro Yamadaf267b812015-02-27 02:26:50 +0900[diff] [blame]74#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
75#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
Masahiro Yamada42ca6982015-02-27 02:26:53 +0900[diff] [blame]76#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
Masahiro Yamada15351632015-02-27 02:26:58 +0900[diff] [blame]77#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
Masahiro Yamada28f40d42015-09-22 00:27:40 +0900[diff] [blame]78/* Pro4 or older */
Masahiro Yamadaf267b812015-02-27 02:26:50 +0900[diff] [blame]79#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
80#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
81#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
82#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]83
Masahiro Yamada28f40d42015-09-22 00:27:40 +0900[diff] [blame]84/* Pro5 or newer */
85#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
86#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
Masahiro Yamada019df872015-09-22 00:27:41 +0900[diff] [blame]87#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
Masahiro Yamada28f40d42015-09-22 00:27:40 +0900[diff] [blame]88#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
89#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
90
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]91/* System reset control register */
92#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
93#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
94#define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014)
95
96#endif /* ARCH_SC_REGS_H */