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Marek Vasut58f17882018-01-08 17:09:45 +01001/*
2 * R-Car Gen3 Clock Pulse Generator
3 *
4 * Copyright (C) 2015-2016 Glider bvba
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
12#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
13
14enum rcar_gen3_clk_types {
15 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
16 CLK_TYPE_GEN3_PLL0,
17 CLK_TYPE_GEN3_PLL1,
18 CLK_TYPE_GEN3_PLL2,
19 CLK_TYPE_GEN3_PLL3,
20 CLK_TYPE_GEN3_PLL4,
21 CLK_TYPE_GEN3_SD,
Marek Vasut58f17882018-01-08 17:09:45 +010022 CLK_TYPE_GEN3_R,
Marek Vasut72242e52019-03-04 21:38:10 +010023 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
24 CLK_TYPE_GEN3_Z,
Marek Vasut58f17882018-01-08 17:09:45 +010025 CLK_TYPE_GEN3_Z2,
Marek Vasut72242e52019-03-04 21:38:10 +010026 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
27 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
28 CLK_TYPE_GEN3_RPCSRC,
29 CLK_TYPE_GEN3_RPC,
30 CLK_TYPE_GEN3_RPCD2,
31
32 /* SoC specific definitions start here */
33 CLK_TYPE_GEN3_SOC_BASE,
Marek Vasut58f17882018-01-08 17:09:45 +010034};
35
36#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
37 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
Marek Vasut72242e52019-03-04 21:38:10 +010038
Marek Vasut58f17882018-01-08 17:09:45 +010039#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
40 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
Marek Vasut72242e52019-03-04 21:38:10 +010041
42#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
43 DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
44 (_parent0) << 16 | (_parent1), \
45 .div = (_div0) << 16 | (_div1), .offset = _md)
46
Marek Vasut58f17882018-01-08 17:09:45 +010047#define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
48 _div_clean) \
Marek Vasut72242e52019-03-04 21:38:10 +010049 DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
50 _parent_clean, _div_clean)
51
52#define DEF_GEN3_OSC(_name, _id, _parent, _div) \
53 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
54
55#define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
56 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
57 (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
58
Adam Forde9a52c42020-06-30 09:30:08 -050059#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
60 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
Marek Vasut58f17882018-01-08 17:09:45 +010061
62struct rcar_gen3_cpg_pll_config {
63 u8 extal_div;
64 u8 pll1_mult;
65 u8 pll1_div;
66 u8 pll3_mult;
67 u8 pll3_div;
Marek Vasut72242e52019-03-04 21:38:10 +010068 u8 osc_prediv;
Marek Vasut58f17882018-01-08 17:09:45 +010069};
70
Marek Vasut72242e52019-03-04 21:38:10 +010071#define CPG_RPCCKCR 0x238
Marek Vasut58f17882018-01-08 17:09:45 +010072#define CPG_RCKCR 0x240
73
74struct gen3_clk_priv {
75 void __iomem *base;
76 struct cpg_mssr_info *info;
77 struct clk clk_extal;
78 struct clk clk_extalr;
Marek Vasut716d7752018-05-31 19:47:42 +020079 bool sscg;
Marek Vasut58f17882018-01-08 17:09:45 +010080 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
81};
82
83int gen3_clk_probe(struct udevice *dev);
84int gen3_clk_remove(struct udevice *dev);
85
86extern const struct clk_ops gen3_clk_ops;
87
88#endif