blob: e0d76ef695d01cf18a856149819aa697ae3e83af [file] [log] [blame]
Enric Balletbò i Serra9d1b2982015-09-07 07:43:20 +02001/*
2 * mux.c
3 *
4 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <asm/arch/sys_proto.h>
11#include <asm/arch/hardware.h>
12#include <asm/arch/mux.h>
13#include <asm/io.h>
14#include <i2c.h>
15#include "board.h"
16
17static struct module_pin_mux uart0_pin_mux[] = {
18 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
19 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
20 {-1},
21};
22
23static struct module_pin_mux uart1_pin_mux[] = {
24 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
25 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
26 {-1},
27};
28
29static struct module_pin_mux uart2_pin_mux[] = {
30 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
31 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
32 {-1},
33};
34
35static struct module_pin_mux uart3_pin_mux[] = {
36 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
37 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
38 {-1},
39};
40
41static struct module_pin_mux uart4_pin_mux[] = {
42 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
43 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
44 {-1},
45};
46
47static struct module_pin_mux uart5_pin_mux[] = {
48 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
49 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
50 {-1},
51};
52
53static struct module_pin_mux mmc0_pin_mux[] = {
54 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
55 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
56 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
57 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
58 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
59 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
60 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
61 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
62 {-1},
63};
64
65static struct module_pin_mux mmc1_pin_mux[] = {
66 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
67 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
68 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
69 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
70 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
71 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
72 {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
73 {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_CD */
74 {-1},
75};
76
77static struct module_pin_mux i2c0_pin_mux[] = {
78 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
79 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
80 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
81 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
82 {-1},
83};
84
85static struct module_pin_mux i2c1_pin_mux[] = {
86 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
87 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
88 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
89 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
90 {-1},
91};
92
93static struct module_pin_mux mii1_pin_mux[] = {
94 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
95 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
96 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
97 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
98 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
99 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
100 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
101 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
102 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
103 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
104 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
105 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
106 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
107 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
108 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
109 {-1},
110};
111
112
113void enable_uart0_pin_mux(void)
114{
115 configure_module_pin_mux(uart0_pin_mux);
116}
117
118void enable_uart1_pin_mux(void)
119{
120 configure_module_pin_mux(uart1_pin_mux);
121}
122
123void enable_uart2_pin_mux(void)
124{
125 configure_module_pin_mux(uart2_pin_mux);
126}
127
128void enable_uart3_pin_mux(void)
129{
130 configure_module_pin_mux(uart3_pin_mux);
131}
132
133void enable_uart4_pin_mux(void)
134{
135 configure_module_pin_mux(uart4_pin_mux);
136}
137
138void enable_uart5_pin_mux(void)
139{
140 configure_module_pin_mux(uart5_pin_mux);
141}
142
143void enable_i2c0_pin_mux(void)
144{
145 configure_module_pin_mux(i2c0_pin_mux);
146}
147
148void enable_board_pin_mux(void)
149{
150 configure_module_pin_mux(i2c1_pin_mux);
151 configure_module_pin_mux(mii1_pin_mux);
152 configure_module_pin_mux(mmc0_pin_mux);
153 configure_module_pin_mux(mmc1_pin_mux);
154}