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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0c7645bde0961c6f44ba265186e3cb50fd5d6247 / . / arch / x86 / dts / chromebook_link.dts
blob: 54f20431728ee2b21453a439278bc424ee6ea5d4 [file] [log] [blame]
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]1/dts-v1/;
2
Bin Meng120c4162014-12-24 13:06:39 +0800[diff] [blame]3/include/ "skeleton.dtsi"
Simon Glass6b44ae62015-11-11 10:05:43 -0700[diff] [blame]4/include/ "keyboard.dtsi"
Bin Meng9ca5a0c2014-12-24 13:06:38 +0800[diff] [blame]5/include/ "serial.dtsi"
Bin Meng93f8a312015-07-15 16:23:39 +0800[diff] [blame]6/include/ "rtc.dtsi"
Bin Meng80af3982015-11-13 00:11:22 -0800[diff] [blame]7/include/ "tsc_timer.dtsi"
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]8
9/ {
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]10 model = "Google Link";
11 compatible = "google,link", "intel,celeron-ivybridge";
12
Simon Glassa9aff2f2015-01-19 22:16:13 -0700[diff] [blame]13 aliases {
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]14 spi0 = "/pci/pch/spi";
Simon Glassa9aff2f2015-01-19 22:16:13 -0700[diff] [blame]15 };
16
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]17 config {
18 silent_console = <0>;
19 };
20
Simon Glassbba22a92016-01-17 16:11:23 -0700[diff] [blame]21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "intel,core-gen3";
28 reg = <0>;
29 intel,apic-id = <0>;
30 };
31
32 cpu@1 {
33 device_type = "cpu";
34 compatible = "intel,core-gen3";
35 reg = <1>;
36 intel,apic-id = <1>;
37 };
38
39 cpu@2 {
40 device_type = "cpu";
41 compatible = "intel,core-gen3";
42 reg = <2>;
43 intel,apic-id = <2>;
44 };
45
46 cpu@3 {
47 device_type = "cpu";
48 compatible = "intel,core-gen3";
49 reg = <3>;
50 intel,apic-id = <3>;
51 };
52
53 };
54
Simon Glassd1259c92014-10-10 07:49:19 -0600[diff] [blame]55 gpioa {
56 compatible = "intel,ich6-gpio";
Simon Glass437c2b72014-11-12 22:42:25 -0700[diff] [blame]57 u-boot,dm-pre-reloc;
Simon Glassd1259c92014-10-10 07:49:19 -0600[diff] [blame]58 reg = <0 0x10>;
59 bank-name = "A";
60 };
61
62 gpiob {
63 compatible = "intel,ich6-gpio";
Simon Glass437c2b72014-11-12 22:42:25 -0700[diff] [blame]64 u-boot,dm-pre-reloc;
Simon Glassd1259c92014-10-10 07:49:19 -0600[diff] [blame]65 reg = <0x30 0x10>;
66 bank-name = "B";
67 };
68
69 gpioc {
70 compatible = "intel,ich6-gpio";
Simon Glass437c2b72014-11-12 22:42:25 -0700[diff] [blame]71 u-boot,dm-pre-reloc;
Simon Glassd1259c92014-10-10 07:49:19 -0600[diff] [blame]72 reg = <0x40 0x10>;
73 bank-name = "C";
74 };
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]75
Bin Meng120c4162014-12-24 13:06:39 +0800[diff] [blame]76 chosen {
77 stdout-path = "/serial";
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]78 };
79
Simon Glass6b44ae62015-11-11 10:05:43 -0700[diff] [blame]80 keyboard {
81 intel,duplicate-por;
82 };
83
Simon Glass65dd74a2014-11-12 22:42:28 -0700[diff] [blame]84 spd {
85 compatible = "memory-spd";
86 #address-cells = <1>;
87 #size-cells = <0>;
88 elpida_4Gb_1600_x16 {
89 reg = <0>;
90 data = [92 10 0b 03 04 19 02 02
91 03 52 01 08 0a 00 fe 00
92 69 78 69 3c 69 11 18 81
93 20 08 3c 3c 01 40 83 81
94 00 00 00 00 00 00 00 00
95 00 00 00 00 00 00 00 00
96 00 00 00 00 00 00 00 00
97 00 00 00 00 0f 11 42 00
98 00 00 00 00 00 00 00 00
99 00 00 00 00 00 00 00 00
100 00 00 00 00 00 00 00 00
101 00 00 00 00 00 00 00 00
102 00 00 00 00 00 00 00 00
103 00 00 00 00 00 00 00 00
104 00 00 00 00 00 02 fe 00
105 11 52 00 00 00 07 7f 37
106 45 42 4a 32 30 55 47 36
107 45 42 55 30 2d 47 4e 2d
108 46 20 30 20 02 fe 00 00
109 00 00 00 00 00 00 00 00
110 00 00 00 00 00 00 00 00
111 00 00 00 00 00 00 00 00
112 00 00 00 00 00 00 00 00
113 00 00 00 00 00 00 00 00
114 00 00 00 00 00 00 00 00
115 00 00 00 00 00 00 00 00
116 00 00 00 00 00 00 00 00
117 00 00 00 00 00 00 00 00
118 00 00 00 00 00 00 00 00
119 00 00 00 00 00 00 00 00
120 00 00 00 00 00 00 00 00
121 00 00 00 00 00 00 00 00];
122 };
123 samsung_4Gb_1600_1.35v_x16 {
124 reg = <1>;
125 data = [92 11 0b 03 04 19 02 02
126 03 11 01 08 0a 00 fe 00
127 69 78 69 3c 69 11 18 81
128 f0 0a 3c 3c 01 40 83 01
129 00 80 00 00 00 00 00 00
130 00 00 00 00 00 00 00 00
131 00 00 00 00 00 00 00 00
132 00 00 00 00 0f 11 02 00
133 00 00 00 00 00 00 00 00
134 00 00 00 00 00 00 00 00
135 00 00 00 00 00 00 00 00
136 00 00 00 00 00 00 00 00
137 00 00 00 00 00 00 00 00
138 00 00 00 00 00 00 00 00
139 00 00 00 00 00 80 ce 01
140 00 00 00 00 00 00 6a 04
141 4d 34 37 31 42 35 36 37
142 34 42 48 30 2d 59 4b 30
143 20 20 00 00 80 ce 00 00
144 00 00 00 00 00 00 00 00
145 00 00 00 00 00 00 00 00
146 00 00 00 00 00 00 00 00
147 00 00 00 00 00 00 00 00
148 00 00 00 00 00 00 00 00
149 00 00 00 00 00 00 00 00
150 00 00 00 00 00 00 00 00
151 00 00 00 00 00 00 00 00
152 00 00 00 00 00 00 00 00
153 00 00 00 00 00 00 00 00
154 00 00 00 00 00 00 00 00
155 00 00 00 00 00 00 00 00
156 00 00 00 00 00 00 00 00];
157 };
158 micron_4Gb_1600_1.35v_x16 {
159 reg = <2>;
160 data = [92 11 0b 03 04 19 02 02
161 03 11 01 08 0a 00 fe 00
162 69 78 69 3c 69 11 18 81
163 20 08 3c 3c 01 40 83 05
164 00 00 00 00 00 00 00 00
165 00 00 00 00 00 00 00 00
166 00 00 00 00 00 00 00 00
167 00 00 00 00 0f 01 02 00
168 00 00 00 00 00 00 00 00
169 00 00 00 00 00 00 00 00
170 00 00 00 00 00 00 00 00
171 00 00 00 00 00 00 00 00
172 00 00 00 00 00 00 00 00
173 00 00 00 00 00 00 00 00
174 00 00 00 00 00 80 2c 00
175 00 00 00 00 00 00 ad 75
176 34 4b 54 46 32 35 36 36
177 34 48 5a 2d 31 47 36 45
178 31 20 45 31 80 2c 00 00
179 00 00 00 00 00 00 00 00
180 00 00 00 00 00 00 00 00
181 00 00 00 00 00 00 00 00
182 ff ff ff ff ff ff ff ff
183 ff ff ff ff ff ff ff ff
184 ff ff ff ff ff ff ff ff
185 ff ff ff ff ff ff ff ff
186 ff ff ff ff ff ff ff ff
187 ff ff ff ff ff ff ff ff
188 ff ff ff ff ff ff ff ff
189 ff ff ff ff ff ff ff ff
190 ff ff ff ff ff ff ff ff
191 ff ff ff ff ff ff ff ff];
192 };
193 };
194
Simon Glassb021e052014-11-14 18:18:36 -0700[diff] [blame]195 pci {
Simon Glasscdc337e2016-01-17 16:11:41 -0700[diff] [blame]196 compatible = "pci-x86";
Simon Glass801f4f12015-03-05 12:25:32 -0700[diff] [blame]197 #address-cells = <3>;
198 #size-cells = <2>;
199 u-boot,dm-pre-reloc;
200 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
201 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
202 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
Simon Glasse40a6e32016-01-17 16:11:15 -0700[diff] [blame]203
204 northbridge@0,0 {
205 reg = <0x00000000 0 0 0 0>;
206 compatible = "intel,bd82x6x-northbridge";
207 u-boot,dm-pre-reloc;
208 };
209
Simon Glassf3e56fe2014-11-14 20:56:37 -0700[diff] [blame]210 gma {
211 compatible = "intel,gma";
212 intel,dp_hotplug = <0 0 0x06>;
213 intel,panel-port-select = <1>;
214 intel,panel-power-cycle-delay = <6>;
215 intel,panel-power-up-delay = <2000>;
216 intel,panel-power-down-delay = <500>;
217 intel,panel-power-backlight-on-delay = <2000>;
218 intel,panel-power-backlight-off-delay = <2000>;
219 intel,cpu-backlight = <0x00000200>;
220 intel,pch-backlight = <0x04000000>;
221 };
222
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]223 pch@1f,0 {
Simon Glassaad78d22015-03-05 12:25:33 -0700[diff] [blame]224 reg = <0x0000f800 0 0 0 0>;
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]225 compatible = "intel,bd82x6x", "intel,pch9";
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]226 u-boot,dm-pre-reloc;
Simon Glass6ddc4fd2014-10-10 07:30:13 -0600[diff] [blame]227 #address-cells = <1>;
228 #size-cells = <1>;
Simon Glass05efc392014-11-14 18:18:37 -0700[diff] [blame]229 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
230 0x80 0x80 0x80 0x80>;
231 intel,gpi-routing = <0 0 0 0 0 0 0 2
232 1 0 0 0 0 0 0 0>;
233 /* Enable EC SMI source */
234 intel,alt-gp-smi-enable = <0x0100>;
Simon Glassf2b85ab2016-01-18 20:19:21 -0700[diff] [blame]235
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]236 spi {
Simon Glassb021e052014-11-14 18:18:36 -0700[diff] [blame]237 #address-cells = <1>;
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]238 #size-cells = <0>;
239 compatible = "intel,ich-spi";
240 spi-flash@0 {
241 #size-cells = <1>;
242 #address-cells = <1>;
243 reg = <0>;
244 compatible = "winbond,w25q64",
245 "spi-flash";
246 memory-map = <0xff800000 0x00800000>;
247 rw-mrc-cache {
248 label = "rw-mrc-cache";
249 reg = <0x003e0000 0x00010000>;
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]250 };
251 };
252 };
253
254 lpc {
255 compatible = "intel,bd82x6x-lpc";
256 #address-cells = <1>;
257 #size-cells = <0>;
Simon Glass4acc83d2016-01-17 16:11:10 -0700[diff] [blame]258 u-boot,dm-pre-reloc;
Simon Glass788cd902016-01-17 16:11:11 -0700[diff] [blame]259 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
Simon Glass90b16d12015-03-26 09:29:29 -0600[diff] [blame]260 cros-ec@200 {
261 compatible = "google,cros-ec";
262 reg = <0x204 1 0x200 1 0x880 0x80>;
263
264 /*
265 * Describes the flash memory within
266 * the EC
267 */
268 #address-cells = <1>;
269 #size-cells = <1>;
270 flash@8000000 {
271 reg = <0x08000000 0x20000>;
272 erase-value = <0xff>;
273 };
Simon Glassb021e052014-11-14 18:18:36 -0700[diff] [blame]274 };
Simon Glass6ddc4fd2014-10-10 07:30:13 -0600[diff] [blame]275 };
276 };
Simon Glassd46f2a62016-01-17 16:11:35 -0700[diff] [blame]277
278 sata@1f,2 {
279 compatible = "intel,pantherpoint-ahci";
280 reg = <0x0000fa00 0 0 0 0>;
281 u-boot,dm-pre-reloc;
282 intel,sata-mode = "ahci";
283 intel,sata-port-map = <1>;
284 intel,sata-port0-gen3-tx = <0x00880a7f>;
285 };
Simon Glass0c7645b2016-01-17 16:11:45 -0700[diff] [blame^]286
287 smbus: smbus@1f,3 {
288 compatible = "intel,ich-i2c";
289 reg = <0x0000fb00 0 0 0 0>;
290 u-boot,dm-pre-reloc;
291 };
Simon Glass6ddc4fd2014-10-10 07:30:13 -0600[diff] [blame]292 };
Simon Glass9c678e12014-11-12 22:42:22 -0700[diff] [blame]293
Simon Glass6e474ea2015-08-22 18:31:37 -0600[diff] [blame]294 tpm {
295 reg = <0xfed40000 0x5000>;
296 compatible = "infineon,slb9635lpc";
297 };
298
Simon Glass9c678e12014-11-12 22:42:22 -0700[diff] [blame]299 microcode {
300 update@0 {
Simon Glasscf29e3e2014-12-15 22:02:40 -0700[diff] [blame]301#include "microcode/m12306a9_0000001b.dtsi"
Simon Glass9c678e12014-11-12 22:42:22 -0700[diff] [blame]302 };
303 };
304
Simon Glass2712f082012-12-03 13:56:51 +0000[diff] [blame]305};