wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * board/config.h - configuration options, board specific |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | /* |
| 32 | * High Level Configuration Options |
| 33 | * (easy to change) |
| 34 | */ |
| 35 | |
| 36 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 37 | #define CONFIG_4xx 1 /* ...member of PPC4xx family */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 38 | #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ |
| 39 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 40 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 41 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 42 | #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 43 | |
| 44 | #define CONFIG_BAUDRATE 9600 |
| 45 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
| 46 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 47 | #undef CONFIG_BOOTARGS |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 48 | #undef CONFIG_BOOTCOMMAND |
| 49 | |
| 50 | #define CONFIG_PREBOOT /* enable preboot variable */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 51 | |
| 52 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 53 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 54 | |
| 55 | #define CONFIG_MII 1 /* MII PHY management */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 56 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 57 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 58 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 59 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ |
stroese | fe389a8 | 2003-08-28 14:17:32 +0000 | [diff] [blame] | 60 | CONFIG_BOOTP_DNS | \ |
| 61 | CONFIG_BOOTP_DNS2 | \ |
| 62 | CONFIG_BOOTP_SEND_HOSTNAME ) |
stroese | 9919f13 | 2003-05-23 11:38:22 +0000 | [diff] [blame] | 63 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 64 | #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
stroese | 9919f13 | 2003-05-23 11:38:22 +0000 | [diff] [blame] | 65 | CFG_CMD_DHCP | \ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 66 | CFG_CMD_PCI | \ |
| 67 | CFG_CMD_IRQ | \ |
| 68 | CFG_CMD_IDE | \ |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 69 | CFG_CMD_FAT | \ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 70 | CFG_CMD_ELF | \ |
stroese | ad10dd9 | 2003-02-14 11:21:23 +0000 | [diff] [blame] | 71 | CFG_CMD_MII | \ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 72 | CFG_CMD_EEPROM ) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 73 | |
| 74 | #define CONFIG_MAC_PARTITION |
| 75 | #define CONFIG_DOS_PARTITION |
| 76 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 77 | #define CONFIG_SUPPORT_VFAT |
| 78 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 79 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 80 | #include <cmd_confdefs.h> |
| 81 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 82 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 83 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 84 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 85 | |
| 86 | /* |
| 87 | * Miscellaneous configurable options |
| 88 | */ |
| 89 | #define CFG_LONGHELP /* undef to save memory */ |
| 90 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 91 | |
| 92 | #undef CFG_HUSH_PARSER /* use "hush" command parser */ |
| 93 | #ifdef CFG_HUSH_PARSER |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 94 | #define CFG_PROMPT_HUSH_PS2 "> " |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 95 | #endif |
| 96 | |
| 97 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 98 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 99 | #else |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 100 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 101 | #endif |
| 102 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 103 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 104 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 105 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 106 | #define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 107 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 108 | #define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 109 | |
| 110 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
| 111 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
| 112 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 113 | #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ |
| 114 | #define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ |
| 115 | #define CFG_BASE_BAUD 691200 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 116 | |
| 117 | /* The following table includes the supported baudrates */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 118 | #define CFG_BAUDRATE_TABLE \ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 119 | { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ |
| 120 | 57600, 115200, 230400, 460800, 921600 } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 121 | |
| 122 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
| 123 | #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
| 124 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 125 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 126 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 127 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
| 128 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 129 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
| 130 | |
| 131 | /*----------------------------------------------------------------------- |
| 132 | * PCI stuff |
| 133 | *----------------------------------------------------------------------- |
| 134 | */ |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 135 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
| 136 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 137 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 138 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 139 | #define CONFIG_PCI /* include pci support */ |
| 140 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
| 141 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 142 | /* resource configuration */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 143 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 144 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 145 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 146 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ |
stroese | ad10dd9 | 2003-02-14 11:21:23 +0000 | [diff] [blame] | 147 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 148 | #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ |
| 149 | |
| 150 | #define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
| 151 | #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ |
| 152 | #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ |
| 153 | #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
| 154 | #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
| 155 | #define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ |
| 156 | #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 157 | #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ |
| 158 | #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ |
| 159 | #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 160 | |
| 161 | /*----------------------------------------------------------------------- |
| 162 | * IDE/ATA stuff |
| 163 | *----------------------------------------------------------------------- |
| 164 | */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 165 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
| 166 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
| 167 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 168 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 169 | #define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ |
| 170 | #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 171 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 172 | #define CFG_ATA_BASE_ADDR 0xF0100000 |
| 173 | #define CFG_ATA_IDE0_OFFSET 0x0000 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 174 | |
| 175 | #define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 176 | #define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 177 | #define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ |
| 178 | |
| 179 | /*----------------------------------------------------------------------- |
| 180 | * Start addresses for the final memory configuration |
| 181 | * (Set up by the startup code) |
| 182 | * Please note that CFG_SDRAM_BASE _must_ start at 0 |
| 183 | */ |
| 184 | #define CFG_SDRAM_BASE 0x00000000 |
| 185 | #define CFG_FLASH_BASE 0xFFFD0000 |
| 186 | #define CFG_MONITOR_BASE CFG_FLASH_BASE |
| 187 | #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ |
| 188 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ |
| 189 | |
| 190 | /* |
| 191 | * For booting Linux, the board info and command line data |
| 192 | * have to be in the first 8 MB of memory, since this is |
| 193 | * the maximum mapped by the Linux kernel during initialization. |
| 194 | */ |
| 195 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 196 | /*----------------------------------------------------------------------- |
| 197 | * FLASH organization |
| 198 | */ |
| 199 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
| 200 | #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ |
| 201 | |
| 202 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 203 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| 204 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 205 | #define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ |
| 206 | #define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ |
| 207 | #define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 208 | /* |
| 209 | * The following defines are added for buggy IOP480 byte interface. |
| 210 | * All other boards should use the standard values (CPCI405 etc.) |
| 211 | */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 212 | #define CFG_FLASH_READ0 0x0000 /* 0 is standard */ |
| 213 | #define CFG_FLASH_READ1 0x0001 /* 1 is standard */ |
| 214 | #define CFG_FLASH_READ2 0x0002 /* 2 is standard */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 215 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 216 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 217 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 218 | #define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ |
| 219 | #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ |
| 220 | #define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ |
| 221 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 222 | #if 1 /* Use NVRAM for environment variables */ |
| 223 | /*----------------------------------------------------------------------- |
| 224 | * NVRAM organization |
| 225 | */ |
| 226 | #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 227 | #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ |
| 228 | #define CFG_ENV_ADDR \ |
| 229 | (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 230 | |
| 231 | #else /* Use EEPROM for environment variables */ |
| 232 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 233 | #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
| 234 | #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ |
| 235 | #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 236 | /* total size of a CAT24WC08 is 1024 bytes */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 237 | #endif |
| 238 | |
| 239 | /*----------------------------------------------------------------------- |
| 240 | * I2C EEPROM (CAT24WC08) for environment |
| 241 | */ |
| 242 | #define CONFIG_HARD_I2C /* I2c with hardware support */ |
| 243 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 244 | #define CFG_I2C_SLAVE 0x7F |
| 245 | |
| 246 | #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 247 | #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
| 248 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 249 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
| 250 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ |
| 251 | /* 16 byte page write mode using*/ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 252 | /* last 4 bits of the address */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 253 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
| 254 | #define CFG_EEPROM_PAGE_WRITE_ENABLE |
| 255 | |
| 256 | /*----------------------------------------------------------------------- |
| 257 | * Cache Configuration |
| 258 | */ |
Wolfgang Denk | 0c8721a | 2005-09-23 11:05:55 +0200 | [diff] [blame^] | 259 | #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 260 | #define CFG_CACHELINE_SIZE 32 /* ... */ |
| 261 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 262 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 263 | #endif |
| 264 | |
| 265 | /* |
| 266 | * Init Memory Controller: |
| 267 | * |
| 268 | * BR0/1 and OR0/1 (FLASH) |
| 269 | */ |
| 270 | |
| 271 | #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ |
| 272 | #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ |
| 273 | |
| 274 | /*----------------------------------------------------------------------- |
| 275 | * External Bus Controller (EBC) Setup |
| 276 | */ |
| 277 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 278 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
| 279 | #define CFG_EBC_PB0AP 0x92015480 |
| 280 | #define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 281 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 282 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
| 283 | #define CFG_EBC_PB1AP 0x92015480 |
| 284 | #define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 285 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 286 | /* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */ |
| 287 | #define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
| 288 | #define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 289 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 290 | /* Memory Bank 3 (CompactFlash IDE) initialization */ |
| 291 | #define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
| 292 | #define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 293 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 294 | /* Memory Bank 4 (NVRAM) initialization */ |
| 295 | #define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ |
| 296 | #define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 297 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 298 | /* Memory Bank 5 (Quart) initialization */ |
| 299 | #define CFG_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ |
| 300 | #define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 301 | |
| 302 | /*----------------------------------------------------------------------- |
| 303 | * FPGA stuff |
| 304 | */ |
| 305 | |
| 306 | /* FPGA program pin configuration */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 307 | #define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ |
| 308 | #define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ |
| 309 | #define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ |
| 310 | #define CFG_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ |
| 311 | #define CFG_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 312 | |
| 313 | /*----------------------------------------------------------------------- |
| 314 | * Definitions for initial stack pointer and data area (in data cache) |
| 315 | */ |
| 316 | #if 1 /* test-only */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 317 | #define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 318 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 319 | #define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 320 | #else |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 321 | #define CFG_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 322 | #endif |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 323 | #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 324 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 325 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 326 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 327 | |
| 328 | |
| 329 | /* |
| 330 | * Internal Definitions |
| 331 | * |
| 332 | * Boot Flags |
| 333 | */ |
| 334 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 335 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 336 | |
| 337 | #endif /* __CONFIG_H */ |