blob: 32216cd50e4bc28dac442e6dcb9290b66e4fca2e [file] [log] [blame]
Wolfgang Denk52568c32009-05-16 10:47:46 +02001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009, DAVE Srl <www.dave.eu>
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk52568c32009-05-16 10:47:46 +02006 */
7
8/*
9 * Aria board configuration file
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_ARIA 1
16/*
17 * Memory map for the ARIA board:
18 *
19 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
20 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
21 * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6
22 * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2
23 * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
24 * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB)
25 * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB)
26 * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB)
27 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
28 */
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_E300 1 /* E300 Family */
34#define CONFIG_MPC512X 1 /* MPC512X family */
35#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
Wolfgang Denk52568c32009-05-16 10:47:46 +020036
Wolfgang Denk2ae18242010-10-06 09:05:45 +020037#define CONFIG_SYS_TEXT_BASE 0xFFF00000
38
Wolfgang Denk52568c32009-05-16 10:47:46 +020039/* video */
40#undef CONFIG_VIDEO
41
42#if defined(CONFIG_VIDEO)
43#define CONFIG_CFB_CONSOLE
44#define CONFIG_VGA_AS_SINGLE_DEVICE
45#endif
46
47/* CONFIG_PCI is defined at config time */
48
49#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
50
Wolfgang Denk52568c32009-05-16 10:47:46 +020051#define CONFIG_MISC_INIT_R
52
53#define CONFIG_SYS_IMMR 0x80000000
54#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
55
56#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
57#define CONFIG_SYS_MEMTEST_END 0x00400000
58
59/*
60 * DDR Setup - manually set all parameters as there's no SPD etc.
61 */
62#define CONFIG_SYS_DDR_SIZE 256 /* MB */
63#define CONFIG_SYS_DDR_BASE 0x00000000
64#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anatolij Gustschinb9947bb2010-04-24 19:27:08 +020065#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
Wolfgang Denk52568c32009-05-16 10:47:46 +020066
Anatolij Gustschin5d937e82010-04-24 19:27:07 +020067#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
68
Wolfgang Denk52568c32009-05-16 10:47:46 +020069/* DDR Controller Configuration
70 *
71 * SYS_CFG:
72 * [31:31] MDDRC Soft Reset: Diabled
73 * [30:30] DRAM CKE pin: Enabled
74 * [29:29] DRAM CLK: Enabled
75 * [28:28] Command Mode: Enabled (For initialization only)
76 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
77 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
78 * [20:19] Read Test: DON'T USE
79 * [18:18] Self Refresh: Enabled
80 * [17:17] 16bit Mode: Disabled
81 * [16:13] Ready Delay: 2
82 * [12:12] Half DQS Delay: Disabled
83 * [11:11] Quarter DQS Delay: Disabled
84 * [10:08] Write Delay: 2
85 * [07:07] Early ODT: Disabled
86 * [06:06] On DIE Termination: Disabled
87 * [05:05] FIFO Overflow Clear: DON'T USE here
88 * [04:04] FIFO Underflow Clear: DON'T USE here
89 * [03:03] FIFO Overflow Pending: DON'T USE here
90 * [02:02] FIFO Underlfow Pending: DON'T USE here
91 * [01:01] FIFO Overlfow Enabled: Enabled
92 * [00:00] FIFO Underflow Enabled: Enabled
93 * TIME_CFG0
94 * [31:16] DRAM Refresh Time: 0 CSB clocks
95 * [15:8] DRAM Command Time: 0 CSB clocks
96 * [07:00] DRAM Precharge Time: 0 CSB clocks
97 * TIME_CFG1
98 * [31:26] DRAM tRFC:
99 * [25:21] DRAM tWR1:
100 * [20:17] DRAM tWRT1:
101 * [16:11] DRAM tDRR:
102 * [10:05] DRAM tRC:
103 * [04:00] DRAM tRAS:
104 * TIME_CFG2
105 * [31:28] DRAM tRCD:
106 * [27:23] DRAM tFAW:
107 * [22:19] DRAM tRTW1:
108 * [18:15] DRAM tCCD:
109 * [14:10] DRAM tRTP:
110 * [09:05] DRAM tRP:
111 * [04:00] DRAM tRPA
112 */
Wolfgang Denk25671c82009-06-14 20:58:48 +0200113#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
114 (1 << 30) | /* CKE */ \
115 (1 << 29) | /* CLK_ON */ \
Martha M Stan054197b2009-09-21 14:07:14 -0400116 (0 << 28) | /* CMD_MODE */ \
Wolfgang Denk25671c82009-06-14 20:58:48 +0200117 (4 << 25) | /* DRAM_ROW_SELECT */ \
118 (3 << 21) | /* DRAM_BANK_SELECT */ \
119 (0 << 18) | /* SELF_REF_EN */ \
120 (0 << 17) | /* 16BIT_MODE */ \
121 (2 << 13) | /* RDLY */ \
122 (0 << 12) | /* HALF_DQS_DLY */ \
123 (1 << 11) | /* QUART_DQS_DLY */ \
124 (2 << 8) | /* WDLY */ \
125 (0 << 7) | /* EARLY_ODT */ \
126 (1 << 6) | /* ON_DIE_TERMINATE */ \
127 (0 << 5) | /* FIFO_OV_CLEAR */ \
128 (0 << 4) | /* FIFO_UV_CLEAR */ \
129 (0 << 1) | /* FIFO_OV_EN */ \
130 (0 << 0) /* FIFO_UV_EN */ \
131 )
132
Martha M Stan054197b2009-09-21 14:07:14 -0400133#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
Wolfgang Denk25671c82009-06-14 20:58:48 +0200134#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
135#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
Wolfgang Denk52568c32009-05-16 10:47:46 +0200136
Martha M Stan054197b2009-09-21 14:07:14 -0400137#define CONFIG_SYS_DDRCMD_NOP 0x01380000
138#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
Wolfgang Denk25671c82009-06-14 20:58:48 +0200139#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
140 (0 << 22) | /* DRAM_CS */ \
141 (0 << 21) | /* DRAM_RAS */ \
142 (0 << 20) | /* DRAM_CAS */ \
143 (0 << 19) | /* DRAM_WEB */ \
144 (1 << 16) | /* DRAM_BS[2:0] */ \
145 (0 << 15) | /* */ \
146 (0 << 12) | /* A12->out */ \
147 (0 << 11) | /* A11->RDQS */ \
148 (0 << 10) | /* A10->DQS# */ \
149 (0 << 7) | /* OCD program */ \
150 (0 << 6) | /* Rtt1 */ \
151 (0 << 3) | /* posted CAS# */ \
152 (0 << 2) | /* Rtt0 */ \
153 (1 << 1) | /* ODS */ \
154 (0 << 0) /* DLL */ \
155 )
156#define CONFIG_SYS_MICRON_EMR2 0x01020000
157#define CONFIG_SYS_MICRON_EMR3 0x01030000
Martha M Stan054197b2009-09-21 14:07:14 -0400158#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
Wolfgang Denk52568c32009-05-16 10:47:46 +0200159#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
Wolfgang Denk25671c82009-06-14 20:58:48 +0200160#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
161 (0 << 22) | /* DRAM_CS */ \
162 (0 << 21) | /* DRAM_RAS */ \
163 (0 << 20) | /* DRAM_CAS */ \
164 (0 << 19) | /* DRAM_WEB */ \
165 (1 << 16) | /* DRAM_BS[2:0] */ \
166 (0 << 15) | /* */ \
167 (0 << 12) | /* A12->out */ \
168 (0 << 11) | /* A11->RDQS */ \
169 (1 << 10) | /* A10->DQS# */ \
170 (7 << 7) | /* OCD program */ \
171 (0 << 6) | /* Rtt1 */ \
172 (0 << 3) | /* posted CAS# */ \
173 (1 << 2) | /* Rtt0 */ \
174 (0 << 1) | /* ODS (Output Drive Strength) */ \
175 (0 << 0) /* DLL */ \
176 )
177
178/*
179 * Backward compatible definitions,
Stefan Roesea47a12b2010-04-15 16:07:28 +0200180 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
Wolfgang Denk25671c82009-06-14 20:58:48 +0200181 */
Martha M Stan054197b2009-09-21 14:07:14 -0400182#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
183#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
184#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
185#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200186
187/* DDR Priority Manager Configuration */
188#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
189#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
190#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
191#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
192#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
193#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
194#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
195#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
196#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
197#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
198#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
199#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
200#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
201#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
202#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
203#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
204#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
205#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
206#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
207#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
208#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
209#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
210#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
211
212/*
213 * NOR FLASH on the Local Bus
214 */
215#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
216#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
217#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */
218#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */
219
220#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
221#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
222#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
223#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */
224
225#undef CONFIG_SYS_FLASH_CHECKSUM
226
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200227/*
228 * NAND FLASH support
229 * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
230 */
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200231#define CONFIG_CMD_NAND /* enable NAND support */
232#define CONFIG_JFFS2_NAND /* with JFFS2 on it */
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200233#define CONFIG_NAND_MPC5121_NFC
234#define CONFIG_SYS_NAND_BASE 0x40000000
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200235#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200236
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200237/*
238 * Configuration parameters for MPC5121 NAND driver
239 */
240#define CONFIG_FSL_NFC_WIDTH 1
241#define CONFIG_FSL_NFC_WRITE_SIZE 2048
242#define CONFIG_FSL_NFC_SPARE_SIZE 64
243#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
244
Wolfgang Denk52568c32009-05-16 10:47:46 +0200245#define CONFIG_SYS_SRAM_BASE 0x30000000
246#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
247
Wolfgang Denk25671c82009-06-14 20:58:48 +0200248/* Make two SRAM regions contiguous */
249#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
250 CONFIG_SYS_SRAM_SIZE)
251#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000252#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE
253#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200254
255#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
256 CONFIG_SYS_ARIA_SRAM_SIZE)
257#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */
258
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000259#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE
260#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE
261
Wolfgang Denk52568c32009-05-16 10:47:46 +0200262#define CONFIG_SYS_CS0_CFG 0x05059150
263#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
264 (5 << 16) | \
265 (1 << 15) | \
266 (0 << 14) | \
267 (0 << 13) | \
268 (1 << 12) | \
269 (0 << 10) | \
270 (3 << 8) | /* 32 bit */ \
271 (0 << 7) | \
272 (1 << 6) | \
273 (1 << 4) | \
274 (0 << 3) | \
275 (0 << 2) | \
276 (0 << 1) | \
277 (0 << 0) \
278 )
279#define CONFIG_SYS_CS6_CFG 0x05059150
280
281/* Use alternative CS timing for CS0 and CS2 */
282#define CONFIG_SYS_CS_ALETIMING 0x00000005
283
284/* Use SRAM for initial stack */
285#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
Wolfgang Denk553f0982010-10-26 13:32:32 +0200286#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200287
Wolfgang Denk553f0982010-10-26 13:32:32 +0200288#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200289 GENERATED_GBL_DATA_SIZE)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200290#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
291
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200292#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Wolfgang Denka6d6d462009-06-14 20:58:51 +0200293#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200294
295#ifdef CONFIG_FSL_DIU_FB
296#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
297#else
298#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
299#endif
300
301/* FPGA */
302#define CONFIG_ARIA_FPGA 1
303
304/*
305 * Serial Port
306 */
307#define CONFIG_CONS_INDEX 1
Wolfgang Denk52568c32009-05-16 10:47:46 +0200308
309/*
310 * Serial console configuration
311 */
312#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
Marek Vasutbfb31272012-09-16 16:07:24 +0200313#define CONFIG_SYS_PSC3
Wolfgang Denk52568c32009-05-16 10:47:46 +0200314#if CONFIG_PSC_CONSOLE != 3
315#error CONFIG_PSC_CONSOLE must be 3
316#endif
317
318#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
319#define CONFIG_SYS_BAUDRATE_TABLE \
320 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
321
322#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
323#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
324#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
325#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
326
327#define CONFIG_CMDLINE_EDITING 1 /* command line history */
328/* Use the HUSH parser */
329#define CONFIG_SYS_HUSH_PARSER
330#ifdef CONFIG_SYS_HUSH_PARSER
Wolfgang Denk52568c32009-05-16 10:47:46 +0200331#endif
332
333/*
334 * PCI
335 */
336#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000337#define CONFIG_PCI_INDIRECT_BRIDGE
Wolfgang Denk52568c32009-05-16 10:47:46 +0200338
339#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
340#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
341#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
342#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
343 CONFIG_SYS_PCI_MEM_SIZE)
344#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
345#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
346#define CONFIG_SYS_PCI_IO_BASE 0x00000000
347#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
348#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */
349
350#define CONFIG_PCI_PNP /* do pci plug-and-play */
351
352#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
353
354#endif
355
356/* I2C */
357#define CONFIG_HARD_I2C /* I2C with hardware support */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200358#define CONFIG_I2C_MULTI_BUS
Wolfgang Denk52568c32009-05-16 10:47:46 +0200359
360/* I2C speed and slave address */
361#define CONFIG_SYS_I2C_SPEED 100000
362#define CONFIG_SYS_I2C_SLAVE 0x7F
363#if 0
364#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
365#endif
366
367/*
368 * IIM - IC Identification Module
369 */
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000370#undef CONFIG_FSL_IIM
Wolfgang Denk52568c32009-05-16 10:47:46 +0200371
372/*
373 * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
374 * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
375 */
376#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
377#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
378#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
379#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
380
381/*
382 * Ethernet configuration
383 */
384#define CONFIG_MPC512x_FEC 1
Wolfgang Denk52568c32009-05-16 10:47:46 +0200385#define CONFIG_PHY_ADDR 0x17
386#define CONFIG_MII 1 /* MII PHY management */
387#define CONFIG_FEC_AN_TIMEOUT 1
388#define CONFIG_HAS_ETH0
389
390/*
391 * Environment
392 */
393#define CONFIG_ENV_IS_IN_FLASH 1
394/* This has to be a multiple of the flash sector size */
395#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
396 CONFIG_SYS_MONITOR_LEN)
397#define CONFIG_ENV_SIZE 0x2000
398#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */
399
400/* Address and size of Redundant Environment Sector */
401#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
402 CONFIG_ENV_SECT_SIZE)
403#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
404
405#define CONFIG_LOADS_ECHO 1
406#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
407
408#include <config_cmd_default.h>
409
410#define CONFIG_CMD_ASKENV
411#define CONFIG_CMD_DHCP
412#define CONFIG_CMD_EEPROM
413#undef CONFIG_CMD_FUSE
414#define CONFIG_CMD_I2C
415#undef CONFIG_CMD_IDE
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200416#define CONFIG_CMD_JFFS2
Wolfgang Denk52568c32009-05-16 10:47:46 +0200417#define CONFIG_CMD_MII
418#define CONFIG_CMD_NFS
419#define CONFIG_CMD_PING
420#define CONFIG_CMD_REGINFO
421
422#if defined(CONFIG_PCI)
423#define CONFIG_CMD_PCI
424#endif
425
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200426#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200427#define CONFIG_DOS_PARTITION
428#define CONFIG_MAC_PARTITION
429#define CONFIG_ISO_PARTITION
430#endif /* defined(CONFIG_CMD_IDE) */
431
432/*
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200433 * Dynamic MTD partition support
434 */
435#define CONFIG_CMD_MTDPARTS
436#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
437#define CONFIG_FLASH_CFI_MTD
438#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
439
440/*
441 * NOR flash layout:
442 *
443 * F8000000 - FEAFFFFF 107 MiB User Data
444 * FEB00000 - FFAFFFFF 16 MiB Root File System
445 * FFB00000 - FFFEFFFF 4 MiB Linux Kernel
446 * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env
447 * FFFC0000 - FFFFFFFF 256 KiB Device Tree
448 *
449 * NAND flash layout: one big partition
450 */
451#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
452 "16m(rootfs)," \
453 "4m(kernel)," \
454 "768k(u-boot)," \
455 "256k(dtb);" \
456 "mpc5121.nand:-(data)"
457
458/*
Wolfgang Denk52568c32009-05-16 10:47:46 +0200459 * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
460 * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
461 * is set to 0xFFFF, watchdog timeouts after about 64s. For details
462 * refer to chapter 36 of the MPC5121e Reference Manual.
463 */
464/* #define CONFIG_WATCHDOG */ /* enable watchdog */
465#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
466
467 /*
468 * Miscellaneous configurable options
469 */
470#define CONFIG_SYS_LONGHELP /* undef to save memory */
471#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Wolfgang Denk52568c32009-05-16 10:47:46 +0200472
473#ifdef CONFIG_CMD_KGDB
474# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
475#else
476# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
477#endif
478
479/* Print Buffer Size */
480#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
481 sizeof(CONFIG_SYS_PROMPT) + 16)
482/* max number of command args */
483#define CONFIG_SYS_MAXARGS 32
484/* Boot Argument Buffer Size */
485#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
486
Wolfgang Denk52568c32009-05-16 10:47:46 +0200487/*
488 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700489 * have to be in the first 256 MB of memory, since this is
Wolfgang Denk52568c32009-05-16 10:47:46 +0200490 * the maximum mapped by the Linux kernel during initialization.
491 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700492#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Wolfgang Denk52568c32009-05-16 10:47:46 +0200493
494/* Cache Configuration */
495#define CONFIG_SYS_DCACHE_SIZE 32768
496#define CONFIG_SYS_CACHELINE_SIZE 32
497#ifdef CONFIG_CMD_KGDB
498#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
499#endif
500
501#define CONFIG_SYS_HID0_INIT 0x000000000
502#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
503 HID0_ICE)
504#define CONFIG_SYS_HID2 HID2_HBE
505
506#define CONFIG_HIGH_BATS 1 /* High BATs supported */
507
Wolfgang Denk52568c32009-05-16 10:47:46 +0200508#ifdef CONFIG_CMD_KGDB
509#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
510#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
511#endif
512
513/*
514 * Environment Configuration
515 */
516#define CONFIG_ENV_OVERWRITE
517#define CONFIG_TIMESTAMP
518
519#define CONFIG_HOSTNAME aria
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000520#define CONFIG_BOOTFILE "aria/uImage"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000521#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
Wolfgang Denk52568c32009-05-16 10:47:46 +0200522
523#define CONFIG_LOADADDR 400000 /* default load addr */
524
525#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
526#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
527
528#define CONFIG_BAUDRATE 115200
529
530#define CONFIG_PREBOOT "echo;" \
531 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
532 "echo"
533
534#define CONFIG_EXTRA_ENV_SETTINGS \
535 "u-boot_addr_r=200000\0" \
536 "kernel_addr_r=600000\0" \
537 "fdt_addr_r=880000\0" \
538 "ramdisk_addr_r=900000\0" \
539 "u-boot_addr=FFF00000\0" \
Wolfgang Denk1f1f82f2009-06-14 20:58:52 +0200540 "kernel_addr=FFB00000\0" \
541 "fdt_addr=FFFC0000\0" \
542 "ramdisk_addr=FEB00000\0" \
Wolfgang Denk52568c32009-05-16 10:47:46 +0200543 "ramdiskfile=aria/uRamdisk\0" \
544 "u-boot=aria/u-boot.bin\0" \
545 "fdtfile=aria/aria.dtb\0" \
546 "netdev=eth0\0" \
547 "consdev=ttyPSC0\0" \
548 "nfsargs=setenv bootargs root=/dev/nfs rw " \
549 "nfsroot=${serverip}:${rootpath}\0" \
550 "ramargs=setenv bootargs root=/dev/ram rw\0" \
551 "addip=setenv bootargs ${bootargs} " \
552 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
553 ":${hostname}:${netdev}:off panic=1\0" \
554 "addtty=setenv bootargs ${bootargs} " \
555 "console=${consdev},${baudrate}\0" \
556 "flash_nfs=run nfsargs addip addtty;" \
557 "bootm ${kernel_addr} - ${fdt_addr}\0" \
558 "flash_self=run ramargs addip addtty;" \
559 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
560 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
561 "tftp ${fdt_addr_r} ${fdtfile};" \
562 "run nfsargs addip addtty;" \
563 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
564 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
565 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
566 "tftp ${fdt_addr_r} ${fdtfile};" \
567 "run ramargs addip addtty;" \
568 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
569 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
570 "update=protect off ${u-boot_addr} +${filesize};" \
571 "era ${u-boot_addr} +${filesize};" \
572 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
573 "upd=run load update\0" \
574 ""
575
576#define CONFIG_BOOTCOMMAND "run flash_self"
577
578#define CONFIG_OF_LIBFDT 1
579#define CONFIG_OF_BOARD_SETUP 1
580#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
581
582#define OF_CPU "PowerPC,5121@0"
583#define OF_SOC_COMPAT "fsl,mpc5121-immr"
584#define OF_TBCLK (bd->bi_busfreq / 4)
585#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
586
587/*-----------------------------------------------------------------------
588 * IDE/ATA stuff
589 *-----------------------------------------------------------------------
590 */
591
592#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
593#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
594#undef CONFIG_IDE_LED /* LED for IDE not supported */
595
596#define CONFIG_IDE_RESET /* reset for IDE supported */
597#define CONFIG_IDE_PREINIT
598
599#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */
600#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */
601
602#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
603#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
604
605/* Offset for data I/O RefMan MPC5121EE Table 28-10 */
606#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
607
608/* Offset for normal register accesses */
609#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
610
611/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */
612#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
613
614/* Interval between registers */
615#define CONFIG_SYS_ATA_STRIDE 4
616
617#define ATA_BASE_ADDR get_pata_base()
618
619/*
620 * Control register bit definitions
621 */
622#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
623#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
624#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
625#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
626#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
627#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
628#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
629#define FSL_ATA_CTRL_IORDY_EN 0x01000000
630
Anatolij Gustschine5f53862013-02-08 00:03:45 +0000631/* Clocks in use */
632#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
633 CLOCK_SCCR1_LPC_EN | \
634 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
635 CLOCK_SCCR1_PSCFIFO_EN | \
636 CLOCK_SCCR1_DDR_EN | \
637 CLOCK_SCCR1_FEC_EN | \
638 CLOCK_SCCR1_NFC_EN | \
639 CLOCK_SCCR1_PATA_EN | \
640 CLOCK_SCCR1_PCI_EN | \
641 CLOCK_SCCR1_TPR_EN)
642
643#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
644 CLOCK_SCCR2_SPDIF_EN | \
645 CLOCK_SCCR2_DIU_EN | \
646 CLOCK_SCCR2_I2C_EN)
647
Wolfgang Denk52568c32009-05-16 10:47:46 +0200648#endif /* __CONFIG_H */