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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0dc78ff857337a82d39d7e4390e317ffbc93097f / . / board / freescale / t4rdb / tlb.c
blob: 474301e2a77e43d86adac3fa58237f2e7ee76d81 [file] [log] [blame]
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800[diff] [blame]1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <asm/mmu.h>
9
10struct fsl_e_tlb_entry tlb_table[] = {
11 /* TLB 0 - for temp stack in cache */
12 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
13 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
14 MAS3_SX|MAS3_SW|MAS3_SR, 0,
15 0, 0, BOOKE_PAGESZ_4K, 0),
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
22 MAS3_SX|MAS3_SW|MAS3_SR, 0,
23 0, 0, BOOKE_PAGESZ_4K, 0),
24 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
25 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
26 MAS3_SX|MAS3_SW|MAS3_SR, 0,
27 0, 0, BOOKE_PAGESZ_4K, 0),
28
29 /* TLB 1 */
30 /* *I*** - Covers boot page */
31#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
32 /*
33 * *I*G - L3SRAM. When L3 is used as 512K SRAM */
34 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
35 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
36 0, 0, BOOKE_PAGESZ_512K, 1),
37#else
38 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
39 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
40 0, 0, BOOKE_PAGESZ_4K, 1),
41#endif
42
43 /* *I*G* - CCSRBAR */
44 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
45 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
46 0, 1, BOOKE_PAGESZ_16M, 1),
47
48 /* *I*G* - Flash, localbus */
49 /* This will be changed to *I*G* after relocation to RAM. */
50 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
52 0, 2, BOOKE_PAGESZ_256M, 1),
53
54 /* *I*G* - PCI */
55 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
56 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57 0, 3, BOOKE_PAGESZ_1G, 1),
58
59 /* *I*G* - PCI */
60 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
61 CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
62 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 4, BOOKE_PAGESZ_256M, 1),
64
65 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
66 CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
67 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, 5, BOOKE_PAGESZ_256M, 1),
69
70 /* *I*G* - PCI I/O */
71 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 6, BOOKE_PAGESZ_256K, 1),
74
75 /* Bman/Qman */
76#ifdef CONFIG_SYS_BMAN_MEM_PHYS
77 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
78 MAS3_SX|MAS3_SW|MAS3_SR, 0,
79 0, 9, BOOKE_PAGESZ_16M, 1),
80 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
81 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
82 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 0, 10, BOOKE_PAGESZ_16M, 1),
84#endif
85#ifdef CONFIG_SYS_QMAN_MEM_PHYS
86 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
87 MAS3_SX|MAS3_SW|MAS3_SR, 0,
88 0, 11, BOOKE_PAGESZ_16M, 1),
89 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
90 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
91 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92 0, 12, BOOKE_PAGESZ_16M, 1),
93#endif
94#ifdef CONFIG_SYS_DCSRBAR_PHYS
95 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
96 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
97 0, 13, BOOKE_PAGESZ_32M, 1),
98#endif
99#ifdef CONFIG_SYS_NAND_BASE
100 /*
101 * *I*G - NAND
102 * entry 14 and 15 has been used hard coded, they will be disabled
103 * in cpu_init_f, so we use entry 16 for nand.
104 */
105 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
106 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
107 0, 16, BOOKE_PAGESZ_64K, 1),
108#endif
Chunhe Lanab06b232014-09-12 14:47:09 +0800[diff] [blame]109#ifdef CONFIG_SYS_CPLD_BASE
110 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
111 MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
112 0, 17, BOOKE_PAGESZ_4K, 1),
113#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800[diff] [blame]114};
115
116int num_tlb_entries = ARRAY_SIZE(tlb_table);