blob: 4a650ce43c214c695f25b31c11b1ce8ae9f71518 [file] [log] [blame]
Haiying Wangd11fec52006-05-26 10:24:48 -05001Freescale MPC8641HPCN board
2===========================
3
4Created 05/24/2006 Haiying Wang
5-------------------------------
6
71. Building U-Boot
8------------------
9The 86xx HPCN code base is known to compile using:
10 Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
11
12 $ make MPC8641HPCN_config
13 Configuring for MPC8641HPCN board...
14
15 $ make
16
17
182. Switch and Jumper Setting
19----------------------------
20Jumpers:
21 J14 Pins 1-2 (near plcc32 socket)
22
23Switches:
24 SW1(1-5) = 01100 CFG_COREPLL = 01000 :: CORE = 2:1
25 01100 :: CORE = 2.5:1
26 10000 :: CORE = 3:1
27 11100 :: CORE = 3.5:1
28 10100 :: CORE = 4:1
29 01110 :: CORE = 4.5:1
30 SW1(6-8) = 001 CFG_SYSCLK = 000 :: SYSCLK = 33MHz
31 001 :: SYSCLK = 40MHz
32
Jon Loeligere10390d2006-10-10 17:06:53 -050033 SW2(1-4) = 1100 CFG_CCBPLL = 0010 :: 2X
Haiying Wangd11fec52006-05-26 10:24:48 -050034 0100 :: 4X
35 0110 :: 6X
36 1000 :: 8X
37 1010 :: 10X
38 1100 :: 12X
39 1110 :: 14X
40 0000 :: 16X
41 SW2(5-8) = 1110 CFG_BOOTLOC = 1110 :: boot 16-bit localbus
42
43 SW3(1-7) = 0011000 CFG_VID = 0011000 :: VCORE = 1.2V
44 0100000 :: VCORE = 1.11V
45 SW3(8) = 0 VCC_PLAT = 0 :: VCC_PLAT = 1.2V
46 1 :: VCC_PLAT = 1.0V
47
48 SW4(1-2) = 11 CFG_HOSTMODE = 11 :: both prots host/root
49 SW4(3-4) = 11 CFG_BOOTSEQ = 11 :: no boot seq
50 SW4(5-8) = 0011 CFG_IOPORT = 0011 :: both PEX
51
52 SW5(1) = 1 CFG_FLASHMAP = 1 :: boot from flash
53 0 :: boot from PromJet
54 SW5(2) = 1 CFG_FLASHBANK = 1 :: swap upper/lower
55 halves (virtual banks)
56 0 :: normal
57 SW5(3) = 0 CFG_FLASHWP = 0 :: not protected
58 SW5(4) = 0 CFG_PORTDIV = 1 :: 2:1 for PD4
59 1:1 for PD6
60 SW5(5-6) = 11 CFG_PIXISOPT = 11 :: s/w determined
61 SW5(7-8) = 11 CFG_LADOPT = 11 :: s/w determined
62
63 SW6(1) = 1 CFG_CPUBOOT = 1 :: no boot holdoff
64 SW6(2) = 1 CFG_BOOTADDR = 1 :: no traslation
65 SW6(3-5) = 000 CFG_REFCLKSEL = 000 :: 100MHZ
66 SW6(6) = 1 CFG_SERROM_ADDR= 1 ::
67 SW6(7) = 1 CFG_MEMDEBUG = 1 ::
68 SW6(8) = 1 CFG_DDRDEBUG = 1 ::
69
70 SW8(1) = 1 ACZ_SYNC = 1 :: 48MHz on TP49
71 SW8(2) = 1 ACB_SYNC = 1 :: THRMTRIP disabled
72 SW8(3) = 1 ACZ_SDOUT = 1 :: p4 mode
73 SW8(4) = 1 ACB_SDOUT = 1 :: PATA freq. = 133MHz
74 SW8(5) = 0 SUSLED = 0 :: SouthBridge Mode
75 SW8(6) = 0 SPREAD = 0 :: REFCLK SSCG Disabled
76 SW8(7) = 1 ACPWR = 1 :: non-battery
77 SW8(8) = 0 CFG_IDWP = 0 :: write enable
78
79
803. Flash U-Boot
81---------------
82The flash range 0xFF800000 to 0xFFFFFFFF can be divided into 2 halves.
83It is possible to use either half to boot using u-boot. Switch 5 bit 2
84is used for this purpose.
85
860xFF800000 to 0xFFBFFFFF - 4MB
870xFFC00000 to 0xFFFFFFFF - 4MB
88When this bit is 0, U-Boot is at 0xFFF00000.
89When this bit is 1, U-Boot is at 0xFFB00000.
90
91Use the above mentioned flash commands to program the other half, and
92use switch 5, bit 2 to alternate between the halves. Note: The booting
93version of U-Boot will always be at 0xFFF00000.
94
95To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
96
97 tftp 1000000 u-boot.bin
98 protect off all
99 erase fff00000 ffffffff
100 cp.b 1000000 fff00100 80000
101
102To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
103
104 tftp 1000000 u-boot.bin
105 erase ffb00000 ffbfffff
106 cp.b 1000000 ffb00100 80000
107
108
1094. Memory Map
110-------------
111
Jon Loeligere10390d2006-10-10 17:06:53 -0500112 Memory Range Device Size
Haiying Wangd11fec52006-05-26 10:24:48 -0500113 ------------ ------ ----
114 0x0000_0000 0x7fff_ffff DDR 2G
115 0x8000_0000 0x9fff_ffff PCI1/PEX1 MEM 512M
116 0xa000_0000 0xafff_ffff PCI2/PEX2 MEM 512M
117 0xf800_0000 0xf80f_ffff CCSR 1M
118 0xf810_0000 0xf81f_ffff PIXIS 1M
119 0xf840_0000 0xf840_3fff Stack space 32K
Haiying Wang9cb3e882006-07-28 12:41:41 -0400120 0xe200_0000 0xe2ff_ffff PCI1/PEX1 IO 16M
121 0xe300_0000 0xe3ff_ffff PCI2/PEX2 IO 16M
Haiying Wangd11fec52006-05-26 10:24:48 -0500122 0xfe00_0000 0xfeff_ffff Flash(alternate)16M
123 0xff00_0000 0xffff_ffff Flash(boot bank)16M