Patrice Chotard | 1056303 | 2018-12-06 11:59:42 +0100 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | |
| 3 | #include <dt-bindings/memory/stm32-sdram.h> |
| 4 | |
Patrice Chotard | a1e384b | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 5 | /{ |
| 6 | clocks { |
| 7 | u-boot,dm-pre-reloc; |
| 8 | }; |
| 9 | |
Patrice Chotard | 1056303 | 2018-12-06 11:59:42 +0100 | [diff] [blame^] | 10 | aliases { |
| 11 | gpio0 = &gpioa; |
| 12 | gpio1 = &gpiob; |
| 13 | gpio2 = &gpioc; |
| 14 | gpio3 = &gpiod; |
| 15 | gpio4 = &gpioe; |
| 16 | gpio5 = &gpiof; |
| 17 | gpio6 = &gpiog; |
| 18 | gpio7 = &gpioh; |
| 19 | gpio8 = &gpioi; |
| 20 | gpio9 = &gpioj; |
| 21 | gpio10 = &gpiok; |
| 22 | mmc0 = &sdmmc1; |
| 23 | }; |
| 24 | |
Patrice Chotard | a1e384b | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 25 | soc { |
| 26 | u-boot,dm-pre-reloc; |
| 27 | pin-controller { |
| 28 | u-boot,dm-pre-reloc; |
| 29 | }; |
Patrice Chotard | 1056303 | 2018-12-06 11:59:42 +0100 | [diff] [blame^] | 30 | |
| 31 | fmc: fmc@52004000 { |
| 32 | compatible = "st,stm32h7-fmc"; |
| 33 | reg = <0x52004000 0x1000>; |
| 34 | clocks = <&rcc FMC_CK>; |
| 35 | |
| 36 | pinctrl-0 = <&fmc_pins>; |
| 37 | pinctrl-names = "default"; |
| 38 | status = "okay"; |
| 39 | |
| 40 | /* |
| 41 | * Memory configuration from sdram datasheet IS42S32800G-6BLI |
| 42 | * firsct bank is bank@0 |
| 43 | * second bank is bank@1 |
| 44 | */ |
| 45 | bank1: bank@1 { |
| 46 | st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4 |
| 47 | CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>; |
| 48 | st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2 |
| 49 | TWR_1 TRCD_1>; |
| 50 | st,sdram-refcount = <1539>; |
| 51 | }; |
| 52 | }; |
| 53 | |
| 54 | sdmmc1: sdmmc@52007000 { |
| 55 | compatible = "st,stm32-sdmmc2"; |
| 56 | reg = <0x52007000 0x1000>; |
| 57 | interrupts = <49>; |
| 58 | clocks = <&rcc SDMMC1_CK>; |
| 59 | resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; |
| 60 | st,idma = <1>; |
| 61 | cap-sd-highspeed; |
| 62 | cap-mmc-highspeed; |
| 63 | }; |
Patrice Chotard | a1e384b | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 64 | }; |
| 65 | }; |
| 66 | |
| 67 | &clk_hse { |
| 68 | u-boot,dm-pre-reloc; |
| 69 | }; |
| 70 | |
Patrice Chotard | a1e384b | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 71 | &clk_i2s { |
| 72 | u-boot,dm-pre-reloc; |
| 73 | }; |
| 74 | |
Patrice Chotard | 1056303 | 2018-12-06 11:59:42 +0100 | [diff] [blame^] | 75 | &clk_lse { |
Patrice Chotard | a1e384b | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 76 | u-boot,dm-pre-reloc; |
| 77 | }; |
| 78 | |
Patrice Chotard | a1e384b | 2017-09-13 18:00:11 +0200 | [diff] [blame] | 79 | |
| 80 | &fmc { |
| 81 | u-boot,dm-pre-reloc; |
| 82 | }; |
| 83 | |
| 84 | &clk_hsi { |
| 85 | u-boot,dm-pre-reloc; |
| 86 | }; |
| 87 | |
| 88 | &clk_csi { |
| 89 | u-boot,dm-pre-reloc; |
| 90 | }; |
| 91 | |
| 92 | &gpioa { |
| 93 | u-boot,dm-pre-reloc; |
| 94 | }; |
| 95 | |
| 96 | &gpiob { |
| 97 | u-boot,dm-pre-reloc; |
| 98 | }; |
| 99 | |
| 100 | &gpioc { |
| 101 | u-boot,dm-pre-reloc; |
| 102 | }; |
| 103 | |
| 104 | &gpiod { |
| 105 | u-boot,dm-pre-reloc; |
| 106 | }; |
| 107 | |
| 108 | &gpioe { |
| 109 | u-boot,dm-pre-reloc; |
| 110 | }; |
| 111 | |
| 112 | &gpiof { |
| 113 | u-boot,dm-pre-reloc; |
| 114 | }; |
| 115 | |
| 116 | &gpiog { |
| 117 | u-boot,dm-pre-reloc; |
| 118 | }; |
| 119 | |
| 120 | &gpioh { |
| 121 | u-boot,dm-pre-reloc; |
| 122 | }; |
| 123 | |
| 124 | &gpioi { |
| 125 | u-boot,dm-pre-reloc; |
| 126 | }; |
| 127 | |
| 128 | &gpioj { |
| 129 | u-boot,dm-pre-reloc; |
| 130 | }; |
| 131 | |
| 132 | &gpiok { |
| 133 | u-boot,dm-pre-reloc; |
| 134 | }; |
Patrice Chotard | 1056303 | 2018-12-06 11:59:42 +0100 | [diff] [blame^] | 135 | |
| 136 | &pinctrl { |
| 137 | fmc_pins: fmc@0 { |
| 138 | pins { |
| 139 | pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>, |
| 140 | <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>, |
| 141 | <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>, |
| 142 | <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>, |
| 143 | <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>, |
| 144 | <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>, |
| 145 | <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>, |
| 146 | |
| 147 | <STM32H7_PE0_FUNC_FMC_NBL0>, |
| 148 | <STM32H7_PE1_FUNC_FMC_NBL1>, |
| 149 | <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>, |
| 150 | <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>, |
| 151 | <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>, |
| 152 | <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>, |
| 153 | <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>, |
| 154 | <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>, |
| 155 | <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>, |
| 156 | <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>, |
| 157 | <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>, |
| 158 | |
| 159 | <STM32H7_PF0_FUNC_FMC_A0>, |
| 160 | <STM32H7_PF1_FUNC_FMC_A1>, |
| 161 | <STM32H7_PF2_FUNC_FMC_A2>, |
| 162 | <STM32H7_PF3_FUNC_FMC_A3>, |
| 163 | <STM32H7_PF4_FUNC_FMC_A4>, |
| 164 | <STM32H7_PF5_FUNC_FMC_A5>, |
| 165 | <STM32H7_PF11_FUNC_FMC_SDNRAS>, |
| 166 | <STM32H7_PF12_FUNC_FMC_A6>, |
| 167 | <STM32H7_PF13_FUNC_FMC_A7>, |
| 168 | <STM32H7_PF14_FUNC_FMC_A8>, |
| 169 | <STM32H7_PF15_FUNC_FMC_A9>, |
| 170 | |
| 171 | <STM32H7_PG0_FUNC_FMC_A10>, |
| 172 | <STM32H7_PG1_FUNC_FMC_A11>, |
| 173 | <STM32H7_PG2_FUNC_FMC_A12>, |
| 174 | <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>, |
| 175 | <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>, |
| 176 | <STM32H7_PG8_FUNC_FMC_SDCLK>, |
| 177 | <STM32H7_PG15_FUNC_FMC_SDNCAS>, |
| 178 | |
| 179 | <STM32H7_PH5_FUNC_FMC_SDNWE>, |
| 180 | <STM32H7_PH6_FUNC_FMC_SDNE1>, |
| 181 | <STM32H7_PH7_FUNC_FMC_SDCKE1>, |
| 182 | <STM32H7_PH8_FUNC_FMC_D16>, |
| 183 | <STM32H7_PH9_FUNC_FMC_D17>, |
| 184 | <STM32H7_PH10_FUNC_FMC_D18>, |
| 185 | <STM32H7_PH11_FUNC_FMC_D19>, |
| 186 | <STM32H7_PH12_FUNC_FMC_D20>, |
| 187 | <STM32H7_PH13_FUNC_FMC_D21>, |
| 188 | <STM32H7_PH14_FUNC_FMC_D22>, |
| 189 | <STM32H7_PH15_FUNC_FMC_D23>, |
| 190 | |
| 191 | <STM32H7_PI0_FUNC_FMC_D24>, |
| 192 | <STM32H7_PI1_FUNC_FMC_D25>, |
| 193 | <STM32H7_PI2_FUNC_FMC_D26>, |
| 194 | <STM32H7_PI3_FUNC_FMC_D27>, |
| 195 | <STM32H7_PI4_FUNC_FMC_NBL2>, |
| 196 | <STM32H7_PI5_FUNC_FMC_NBL3>, |
| 197 | <STM32H7_PI6_FUNC_FMC_D28>, |
| 198 | <STM32H7_PI7_FUNC_FMC_D29>, |
| 199 | <STM32H7_PI9_FUNC_FMC_D30>, |
| 200 | <STM32H7_PI10_FUNC_FMC_D31>; |
| 201 | |
| 202 | slew-rate = <3>; |
| 203 | }; |
| 204 | }; |
| 205 | |
| 206 | pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 { |
| 207 | pins { |
| 208 | pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>, |
| 209 | <STM32H7_PB9_FUNC_SDMMC1_CDIR>, |
| 210 | <STM32H7_PC6_FUNC_SDMMC1_D0DIR>, |
| 211 | <STM32H7_PC7_FUNC_SDMMC1_D123DIR>; |
| 212 | drive-push-pull; |
| 213 | slew-rate = <3>; |
| 214 | }; |
| 215 | }; |
| 216 | |
| 217 | sdmmc1_pins: sdmmc@0 { |
| 218 | pins { |
| 219 | pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>, |
| 220 | <STM32H7_PC9_FUNC_SDMMC1_D1>, |
| 221 | <STM32H7_PC10_FUNC_SDMMC1_D2>, |
| 222 | <STM32H7_PC11_FUNC_SDMMC1_D3>, |
| 223 | <STM32H7_PC12_FUNC_SDMMC1_CK>, |
| 224 | <STM32H7_PD2_FUNC_SDMMC1_CMD>; |
| 225 | |
| 226 | slew-rate = <3>; |
| 227 | drive-push-pull; |
| 228 | bias-disable; |
| 229 | }; |
| 230 | }; |
| 231 | }; |
| 232 | |
| 233 | &pwrcfg { |
| 234 | u-boot,dm-pre-reloc; |
| 235 | }; |
| 236 | |
| 237 | &rcc { |
| 238 | u-boot,dm-pre-reloc; |
| 239 | }; |