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Andy Fleming063c1262011-04-08 02:10:54 -05001/*
Claudiu Manoil5be00a02013-09-30 12:44:43 +03002 * Copyright 2009-2010, 2013 Freescale Semiconductor, Inc.
Andy Fleming063c1262011-04-08 02:10:54 -05003 * Jun-jie Zhang <b18070@freescale.com>
4 * Mingkai Hu <Mingkai.hu@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming063c1262011-04-08 02:10:54 -05007 */
8#include <common.h>
9#include <miiphy.h>
10#include <phy.h>
11#include <fsl_mdio.h>
12#include <asm/io.h>
13#include <asm/errno.h>
Andy Fleming063c1262011-04-08 02:10:54 -050014
Claudiu Manoil5be00a02013-09-30 12:44:43 +030015void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
Andy Fleming063c1262011-04-08 02:10:54 -050016 int dev_addr, int regnum, int value)
17{
18 int timeout = 1000000;
19
20 out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
21 out_be32(&phyregs->miimcon, value);
Alison Wangd2614ea2014-09-05 13:52:37 +080022 /* Memory barrier */
23 mb();
Andy Fleming063c1262011-04-08 02:10:54 -050024
25 while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--)
26 ;
27}
28
Claudiu Manoil5be00a02013-09-30 12:44:43 +030029int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
Andy Fleming063c1262011-04-08 02:10:54 -050030 int dev_addr, int regnum)
31{
32 int value;
33 int timeout = 1000000;
34
35 /* Put the address of the phy, and the register
36 * number into MIIMADD */
37 out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
38
39 /* Clear the command register, and wait */
40 out_be32(&phyregs->miimcom, 0);
Alison Wangd2614ea2014-09-05 13:52:37 +080041 /* Memory barrier */
42 mb();
Andy Fleming063c1262011-04-08 02:10:54 -050043
44 /* Initiate a read command, and wait */
45 out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
Alison Wangd2614ea2014-09-05 13:52:37 +080046 /* Memory barrier */
47 mb();
Andy Fleming063c1262011-04-08 02:10:54 -050048
49 /* Wait for the the indication that the read is done */
50 while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
51 && timeout--)
52 ;
53
54 /* Grab the value read from the PHY */
55 value = in_be32(&phyregs->miimstat);
56
57 return value;
58}
59
60static int fsl_pq_mdio_reset(struct mii_dev *bus)
61{
Claudiu Manoil5be00a02013-09-30 12:44:43 +030062 struct tsec_mii_mng __iomem *regs =
63 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming063c1262011-04-08 02:10:54 -050064
65 /* Reset MII (due to new addresses) */
66 out_be32(&regs->miimcfg, MIIMCFG_RESET_MGMT);
67
68 out_be32(&regs->miimcfg, MIIMCFG_INIT_VALUE);
69
70 while (in_be32(&regs->miimind) & MIIMIND_BUSY)
71 ;
72
73 return 0;
74}
75
76int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
77{
Claudiu Manoil5be00a02013-09-30 12:44:43 +030078 struct tsec_mii_mng __iomem *phyregs =
79 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming063c1262011-04-08 02:10:54 -050080
81 return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
82}
83
84int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
85 u16 value)
86{
Claudiu Manoil5be00a02013-09-30 12:44:43 +030087 struct tsec_mii_mng __iomem *phyregs =
88 (struct tsec_mii_mng __iomem *)bus->priv;
Andy Fleming063c1262011-04-08 02:10:54 -050089
90 tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
91
92 return 0;
93}
94
95int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
96{
97 struct mii_dev *bus = mdio_alloc();
98
99 if (!bus) {
100 printf("Failed to allocate FSL MDIO bus\n");
101 return -1;
102 }
103
104 bus->read = tsec_phy_read;
105 bus->write = tsec_phy_write;
106 bus->reset = fsl_pq_mdio_reset;
107 sprintf(bus->name, info->name);
108
Claudiu Manoil5be00a02013-09-30 12:44:43 +0300109 bus->priv = (void *)info->regs;
Andy Fleming063c1262011-04-08 02:10:54 -0500110
111 return mdio_register(bus);
112}