Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Xilinx Zynq GPIO device driver |
| 4 | * |
| 5 | * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu> |
| 6 | * |
| 7 | * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c) |
| 8 | * Copyright (C) 2009 - 2014 Xilinx, Inc. |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <asm/gpio.h> |
| 13 | #include <asm/io.h> |
Masahiro Yamada | 1221ce4 | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 14 | #include <linux/errno.h> |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 15 | #include <dm.h> |
| 16 | #include <fdtdec.h> |
| 17 | |
Siva Durga Prasad Paladugu | f17abca | 2016-03-10 16:27:42 +0530 | [diff] [blame] | 18 | /* Maximum banks */ |
| 19 | #define ZYNQ_GPIO_MAX_BANK 4 |
| 20 | |
| 21 | #define ZYNQ_GPIO_BANK0_NGPIO 32 |
| 22 | #define ZYNQ_GPIO_BANK1_NGPIO 22 |
| 23 | #define ZYNQ_GPIO_BANK2_NGPIO 32 |
| 24 | #define ZYNQ_GPIO_BANK3_NGPIO 32 |
| 25 | |
| 26 | #define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \ |
| 27 | ZYNQ_GPIO_BANK1_NGPIO + \ |
| 28 | ZYNQ_GPIO_BANK2_NGPIO + \ |
| 29 | ZYNQ_GPIO_BANK3_NGPIO) |
| 30 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 31 | #define ZYNQMP_GPIO_MAX_BANK 6 |
| 32 | |
| 33 | #define ZYNQMP_GPIO_BANK0_NGPIO 26 |
| 34 | #define ZYNQMP_GPIO_BANK1_NGPIO 26 |
| 35 | #define ZYNQMP_GPIO_BANK2_NGPIO 26 |
| 36 | #define ZYNQMP_GPIO_BANK3_NGPIO 32 |
| 37 | #define ZYNQMP_GPIO_BANK4_NGPIO 32 |
| 38 | #define ZYNQMP_GPIO_BANK5_NGPIO 32 |
| 39 | |
| 40 | #define ZYNQMP_GPIO_NR_GPIOS 174 |
| 41 | |
| 42 | #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0 |
| 43 | #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \ |
| 44 | ZYNQ##str##_GPIO_BANK0_NGPIO - 1) |
| 45 | #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1) |
| 46 | #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \ |
| 47 | ZYNQ##str##_GPIO_BANK1_NGPIO - 1) |
| 48 | #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1) |
| 49 | #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \ |
| 50 | ZYNQ##str##_GPIO_BANK2_NGPIO - 1) |
| 51 | #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1) |
| 52 | #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \ |
| 53 | ZYNQ##str##_GPIO_BANK3_NGPIO - 1) |
| 54 | #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1) |
| 55 | #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \ |
| 56 | ZYNQ##str##_GPIO_BANK4_NGPIO - 1) |
| 57 | #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1) |
| 58 | #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \ |
| 59 | ZYNQ##str##_GPIO_BANK5_NGPIO - 1) |
Siva Durga Prasad Paladugu | f17abca | 2016-03-10 16:27:42 +0530 | [diff] [blame] | 60 | |
| 61 | /* Register offsets for the GPIO device */ |
| 62 | /* LSW Mask & Data -WO */ |
| 63 | #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) |
| 64 | /* MSW Mask & Data -WO */ |
| 65 | #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK)) |
| 66 | /* Data Register-RW */ |
| 67 | #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK)) |
| 68 | /* Direction mode reg-RW */ |
| 69 | #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK)) |
| 70 | /* Output enable reg-RW */ |
| 71 | #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK)) |
| 72 | /* Interrupt mask reg-RO */ |
| 73 | #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK)) |
| 74 | /* Interrupt enable reg-WO */ |
| 75 | #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK)) |
| 76 | /* Interrupt disable reg-WO */ |
| 77 | #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK)) |
| 78 | /* Interrupt status reg-RO */ |
| 79 | #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK)) |
| 80 | /* Interrupt type reg-RW */ |
| 81 | #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK)) |
| 82 | /* Interrupt polarity reg-RW */ |
| 83 | #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK)) |
| 84 | /* Interrupt on any, reg-RW */ |
| 85 | #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK)) |
| 86 | |
| 87 | /* Disable all interrupts mask */ |
| 88 | #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF |
| 89 | |
| 90 | /* Mid pin number of a bank */ |
| 91 | #define ZYNQ_GPIO_MID_PIN_NUM 16 |
| 92 | |
| 93 | /* GPIO upper 16 bit mask */ |
| 94 | #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 |
| 95 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 96 | struct zynq_gpio_platdata { |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 97 | phys_addr_t base; |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 98 | const struct zynq_platform_data *p_data; |
| 99 | }; |
| 100 | |
| 101 | /** |
| 102 | * struct zynq_platform_data - zynq gpio platform data structure |
| 103 | * @label: string to store in gpio->label |
| 104 | * @ngpio: max number of gpio pins |
| 105 | * @max_bank: maximum number of gpio banks |
| 106 | * @bank_min: this array represents bank's min pin |
| 107 | * @bank_max: this array represents bank's max pin |
| 108 | */ |
| 109 | struct zynq_platform_data { |
| 110 | const char *label; |
| 111 | u16 ngpio; |
Michal Simek | 01fcf01 | 2018-06-13 13:22:08 +0200 | [diff] [blame] | 112 | u32 max_bank; |
| 113 | u32 bank_min[ZYNQMP_GPIO_MAX_BANK]; |
| 114 | u32 bank_max[ZYNQMP_GPIO_MAX_BANK]; |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 115 | }; |
| 116 | |
| 117 | static const struct zynq_platform_data zynqmp_gpio_def = { |
| 118 | .label = "zynqmp_gpio", |
| 119 | .ngpio = ZYNQMP_GPIO_NR_GPIOS, |
| 120 | .max_bank = ZYNQMP_GPIO_MAX_BANK, |
| 121 | .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP), |
| 122 | .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP), |
| 123 | .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP), |
| 124 | .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP), |
| 125 | .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP), |
| 126 | .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP), |
| 127 | .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP), |
| 128 | .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP), |
| 129 | .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP), |
| 130 | .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP), |
| 131 | .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP), |
| 132 | .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP), |
| 133 | }; |
| 134 | |
| 135 | static const struct zynq_platform_data zynq_gpio_def = { |
| 136 | .label = "zynq_gpio", |
| 137 | .ngpio = ZYNQ_GPIO_NR_GPIOS, |
| 138 | .max_bank = ZYNQ_GPIO_MAX_BANK, |
| 139 | .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), |
| 140 | .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(), |
| 141 | .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(), |
| 142 | .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(), |
| 143 | .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(), |
| 144 | .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(), |
| 145 | .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(), |
| 146 | .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(), |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 147 | }; |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 148 | |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 149 | /** |
| 150 | * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank |
| 151 | * for a given pin in the GPIO device |
| 152 | * @pin_num: gpio pin number within the device |
| 153 | * @bank_num: an output parameter used to return the bank number of the gpio |
| 154 | * pin |
| 155 | * @bank_pin_num: an output parameter used to return pin number within a bank |
| 156 | * for the given gpio pin |
| 157 | * |
| 158 | * Returns the bank number and pin offset within the bank. |
| 159 | */ |
| 160 | static inline void zynq_gpio_get_bank_pin(unsigned int pin_num, |
| 161 | unsigned int *bank_num, |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 162 | unsigned int *bank_pin_num, |
| 163 | struct udevice *dev) |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 164 | { |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 165 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Michal Simek | 01fcf01 | 2018-06-13 13:22:08 +0200 | [diff] [blame] | 166 | u32 bank; |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 167 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 168 | for (bank = 0; bank < platdata->p_data->max_bank; bank++) { |
| 169 | if (pin_num >= platdata->p_data->bank_min[bank] && |
| 170 | pin_num <= platdata->p_data->bank_max[bank]) { |
| 171 | *bank_num = bank; |
| 172 | *bank_pin_num = pin_num - |
| 173 | platdata->p_data->bank_min[bank]; |
| 174 | return; |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 175 | } |
| 176 | } |
| 177 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 178 | if (bank >= platdata->p_data->max_bank) { |
Michal Simek | 946205a | 2018-07-12 12:30:34 +0200 | [diff] [blame] | 179 | printf("Invalid bank and pin num\n"); |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 180 | *bank_num = 0; |
| 181 | *bank_pin_num = 0; |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 182 | } |
| 183 | } |
| 184 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 185 | static int gpio_is_valid(unsigned gpio, struct udevice *dev) |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 186 | { |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 187 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 188 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 189 | return gpio < platdata->p_data->ngpio; |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 190 | } |
| 191 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 192 | static int check_gpio(unsigned gpio, struct udevice *dev) |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 193 | { |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 194 | if (!gpio_is_valid(gpio, dev)) { |
Andrea Scian | d37c628 | 2015-03-20 16:00:25 +0100 | [diff] [blame] | 195 | printf("ERROR : check_gpio: invalid GPIO %d\n", gpio); |
| 196 | return -1; |
| 197 | } |
| 198 | return 0; |
| 199 | } |
| 200 | |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 201 | static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio) |
| 202 | { |
| 203 | u32 data; |
| 204 | unsigned int bank_num, bank_pin_num; |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 205 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 206 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 207 | if (check_gpio(gpio, dev) < 0) |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 208 | return -1; |
| 209 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 210 | zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 211 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 212 | data = readl(platdata->base + |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 213 | ZYNQ_GPIO_DATA_RO_OFFSET(bank_num)); |
| 214 | |
| 215 | return (data >> bank_pin_num) & 1; |
| 216 | } |
| 217 | |
| 218 | static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value) |
| 219 | { |
| 220 | unsigned int reg_offset, bank_num, bank_pin_num; |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 221 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 222 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 223 | if (check_gpio(gpio, dev) < 0) |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 224 | return -1; |
| 225 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 226 | zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 227 | |
| 228 | if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) { |
| 229 | /* only 16 data bits in bit maskable reg */ |
| 230 | bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM; |
| 231 | reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num); |
| 232 | } else { |
| 233 | reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num); |
| 234 | } |
| 235 | |
| 236 | /* |
| 237 | * get the 32 bit value to be written to the mask/data register where |
| 238 | * the upper 16 bits is the mask and lower 16 bits is the data |
| 239 | */ |
| 240 | value = !!value; |
| 241 | value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) & |
| 242 | ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK); |
| 243 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 244 | writel(value, platdata->base + reg_offset); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 245 | |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio) |
| 250 | { |
| 251 | u32 reg; |
| 252 | unsigned int bank_num, bank_pin_num; |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 253 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 254 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 255 | if (check_gpio(gpio, dev) < 0) |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 256 | return -1; |
| 257 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 258 | zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 259 | |
| 260 | /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ |
| 261 | if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) |
| 262 | return -1; |
| 263 | |
| 264 | /* clear the bit in direction mode reg to set the pin as input */ |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 265 | reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 266 | reg &= ~BIT(bank_pin_num); |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 267 | writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio, |
| 273 | int value) |
| 274 | { |
| 275 | u32 reg; |
| 276 | unsigned int bank_num, bank_pin_num; |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 277 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 278 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 279 | if (check_gpio(gpio, dev) < 0) |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 280 | return -1; |
| 281 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 282 | zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 283 | |
| 284 | /* set the GPIO pin as output */ |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 285 | reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 286 | reg |= BIT(bank_pin_num); |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 287 | writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 288 | |
| 289 | /* configure the output enable reg for the pin */ |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 290 | reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 291 | reg |= BIT(bank_pin_num); |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 292 | writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 293 | |
| 294 | /* set the state of the pin */ |
| 295 | gpio_set_value(gpio, value); |
| 296 | return 0; |
| 297 | } |
| 298 | |
Michal Simek | a6b9587 | 2016-03-04 15:56:50 +0100 | [diff] [blame] | 299 | static int zynq_gpio_get_function(struct udevice *dev, unsigned offset) |
| 300 | { |
| 301 | u32 reg; |
| 302 | unsigned int bank_num, bank_pin_num; |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 303 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Michal Simek | a6b9587 | 2016-03-04 15:56:50 +0100 | [diff] [blame] | 304 | |
| 305 | if (check_gpio(offset, dev) < 0) |
| 306 | return -1; |
| 307 | |
| 308 | zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev); |
| 309 | |
| 310 | /* set the GPIO pin as output */ |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 311 | reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); |
Michal Simek | a6b9587 | 2016-03-04 15:56:50 +0100 | [diff] [blame] | 312 | reg &= BIT(bank_pin_num); |
| 313 | if (reg) |
| 314 | return GPIOF_OUTPUT; |
| 315 | else |
| 316 | return GPIOF_INPUT; |
| 317 | } |
| 318 | |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 319 | static const struct dm_gpio_ops gpio_zynq_ops = { |
| 320 | .direction_input = zynq_gpio_direction_input, |
| 321 | .direction_output = zynq_gpio_direction_output, |
| 322 | .get_value = zynq_gpio_get_value, |
| 323 | .set_value = zynq_gpio_set_value, |
Michal Simek | a6b9587 | 2016-03-04 15:56:50 +0100 | [diff] [blame] | 324 | .get_function = zynq_gpio_get_function, |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 325 | }; |
| 326 | |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 327 | static const struct udevice_id zynq_gpio_ids[] = { |
| 328 | { .compatible = "xlnx,zynq-gpio-1.0", |
| 329 | .data = (ulong)&zynq_gpio_def}, |
| 330 | { .compatible = "xlnx,zynqmp-gpio-1.0", |
| 331 | .data = (ulong)&zynqmp_gpio_def}, |
| 332 | { } |
| 333 | }; |
| 334 | |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 335 | static int zynq_gpio_probe(struct udevice *dev) |
| 336 | { |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 337 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 338 | struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
Michal Simek | 312dd1c | 2018-08-02 12:58:54 +0200 | [diff] [blame] | 339 | const void *label_ptr; |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 340 | |
Michal Simek | 312dd1c | 2018-08-02 12:58:54 +0200 | [diff] [blame] | 341 | label_ptr = dev_read_prop(dev, "label", NULL); |
| 342 | if (label_ptr) { |
| 343 | uc_priv->bank_name = strdup(label_ptr); |
| 344 | if (!uc_priv->bank_name) |
| 345 | return -ENOMEM; |
| 346 | } else { |
| 347 | uc_priv->bank_name = dev->name; |
| 348 | } |
Michal Simek | 0d6fabb | 2018-06-21 13:58:56 +0200 | [diff] [blame] | 349 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 350 | if (platdata->p_data) |
| 351 | uc_priv->gpio_count = platdata->p_data->ngpio; |
Siva Durga Prasad Paladugu | 404a00c | 2016-03-10 16:27:43 +0530 | [diff] [blame] | 352 | |
| 353 | return 0; |
| 354 | } |
| 355 | |
| 356 | static int zynq_gpio_ofdata_to_platdata(struct udevice *dev) |
| 357 | { |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 358 | struct zynq_gpio_platdata *platdata = dev_get_platdata(dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 359 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 360 | platdata->base = (phys_addr_t)dev_read_addr(dev); |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 361 | |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 362 | platdata->p_data = |
| 363 | (struct zynq_platform_data *)dev_get_driver_data(dev); |
Michal Simek | 0df9bea | 2018-07-12 10:58:04 +0200 | [diff] [blame] | 364 | |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 365 | return 0; |
| 366 | } |
| 367 | |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 368 | U_BOOT_DRIVER(gpio_zynq) = { |
| 369 | .name = "gpio_zynq", |
| 370 | .id = UCLASS_GPIO, |
| 371 | .ops = &gpio_zynq_ops, |
| 372 | .of_match = zynq_gpio_ids, |
| 373 | .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata, |
| 374 | .probe = zynq_gpio_probe, |
Vipul Kumar | 0f07257 | 2018-07-20 14:36:49 +0530 | [diff] [blame] | 375 | .platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata), |
Siva Durga Prasad Paladugu | 68c7026 | 2016-03-10 16:27:38 +0530 | [diff] [blame] | 376 | }; |